X9251_07 Datasheet, PDF (8/20 Pages) Intersil Corporation – Quad Digitally-Controlled (XDCP™) Potentiometer

X9251
Increment/Decrement Command
The final command is Increment/Decrement (See Figures 6
and 7). The Increment/Decrement command is different from
the other commands. Once the command is issued and the
X9251 has responded with an Acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCK clock pulse (t_HIGH) while SI is HIGH, the
selected wiper moves one wiper position towards the R_H
terminal. Similarly, for each SCK clock pulse while SI is
LOW, the selected wiper moves one wiper position towards
the R_L terminal. A detailed illustration of the sequence and
timing for this operation are shown. See Instruction format
for more details.
CS
SCK
SI
0 1 0 10
ID3 ID2 ID1 ID0 0
DEVICE ID
0
0 ^{A1 A0} I3 I2 I1 I0 RB RA P1 P0
INTERNAL
ADDRESS
INSTRUCTION REGISTER DCP/WCR
OPCODE
ADDRESS ADDRESS
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0 1 0 1 00
ID3 ID2 ID1 ID0 _{0 0 A1 A0}
I3 I2 I1 I0 RB RA ^P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
DEVICE ID
INTERNAL
ADDRESS
INSTRUCTION REGISTER DCP/WCR
OPCODE
ADDRESS ADDRESS
DATA FOR WCR[7:0] OR DR[7:0]
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE
CS
SCK
SI
0 1 0 1 00
ID3 ID2 ID1 ID0 _{0 0} A1 A0
I3 I2 I1 I0 RB RA P1 P0
XXXX XXXX
DON’T CARE
DEVICE ID
INTERNAL
ADDRESS
INSTRUCTION REGISTER DCP/WCR
OPCODE ADDRESS ADDRESS
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
OR
DATA REGISTER BIT [7:0]
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE
8
FN8166.5
April 13, 2007