X9251_07 Datasheet, PDF (3/20 Pages) Intersil Corporation – Quad Digitally-Controlled (XDCP™) Potentiometer

X9251
Circuit Level Applications
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
circuits
System Level Applications
• Adjust the contrast in LCD displays
• Control the power level of LED transmitters in
communication systems
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless
systems
• Set the operating points in temperature control
systems
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
Pinout
X9251
(24 LD SOIC/TSSOP)
TOP VIEW
SO
A0
R_W3
R_H3
R_L3
NC
V_CC
R_L0
R_H0
R_W0
CS
WP
1
24
2
23
3
22
4
21
5
20
6
19
X9251
7
18
8
17
9
16
10
15
11
14
12
13
HOLD
SCK
R_L2
R_H2
R_W2
NC
V_SS
R_W1
R_H1
R_L1
A1
SI
Pin Assignments
PIN
(SOIC) SYMBOL
FUNCTION
1
SO Serial Data Output for SPI bus
2
A0 Device Address for SPI bus. (See Note 1)
3
R_W3 Wiper Terminal of DCP3
4
R_H3 High Terminal of DCP3
5
R_L3 Low Terminal of DCP3
7
V_CC System Supply Voltage
8
R_L0 Low Terminal of DCP0
9
R_H0 High Terminal of DCP0
10
R_W0 Wiper Terminal of DCP0
11
CS SPI bus. Chip Select active low input
12
WP Hardware Write Protect - active low
13
SI Serial Data Input for SPI bus
14
A1 Device Address for SPI bus. (See Note 1)
15
R_L1 Low Terminal of DCP1
16
R_H1 High Terminal of DCP1
17
R_W1 Wiper Terminal of DCP1
18
V_SS System Ground
20
R_W2 Wiper Terminal of DCP2
21
R_H2 High Terminal of DCP2
22
R_L2 Low Terminal of DCP2
23
SCK Serial Clock for SPI bus
24
HOLD Device select. Pauses the SPI serial bus.
6, 19
NC No Connect
NOTE:
1. A0 and A1 device address pins must be tied to a logic level.
3
FN8166.5
April 13, 2007