X80120 Datasheet, PDF (8/17 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Dual Programmable Time Delay with Local/Remote Voltage Monitors

X80120, X80121
Pin Descriptions
PIN
NAME
DESCRIPTION
1
V4GDO V4 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V4MON is less than V_REF4
and goes LOW when V4MON is greater than V_REF4. There is user selectable delay circuitry on this pin.
2
V4MON V4 Voltage Monitor Input. Second voltage monitor pin. If unused connect to V_CC.
3
DNC
Do Not Connect
4
V_CC
Connect to V_CC.
5
DNC
Do Not Connect.
6
V_P
EEPROM programming Voltage.
7
V_CC
Connect to V_CC.
8
DNC
Do Not Connect.
9
A1
Address Select Input. It has an internal pull-down resistor. (>10MΩ typical)
The A0 and A1 bits allow for up to 4 X80120 devices to be used on the same SMBus serial interface.
10
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and
may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input
buffer is always active (not gated).
11
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
12
V1MON V1 Voltage Monitor Input. First voltage monitor pin. If unused connect to V_CC.
13
V1GDO V1 Voltage Good Delay Output (Active LOW). This open drain output goes HIGH when V1MON is less than V_REF1
and goes LOW when V1MON is greater than V_REF1. There is user selectable delay circuitry on this pin.
14
RESET RESET Output. This open drain pin is an active LOW output. This pin will be active until all ViGDO pins go inactive and
the power sequencing is complete. This pin will be released after a programmable delay.
15
WP
Write Protect. Input Pin. WP HIGH (in conjunction with WPEN bit=1) prevents writes to any memory location in the
device. It has an internal pull-down resistor. (>10MΩ typical)
16
MR
Manual Reset. Pulling the MR pin HIGH initiates a RESET. The MR signal must be held HIGH for 5µsecs. It has an
internal pull-down resistor. (>10MΩ typical)
17
V_SS
Ground Input.
18
NC
No Connect. No internal connections.
19
A0
Address Select Input. It has an internal pull-down resistor. (>10MΩ typical) The A0 and A1 bits allow for up to 4
X80120 devices to be used on the same SMBus serial interface.
20
V_CC
Supply Voltage.
Functional Description
Power On Reset and System Reset With Delay
Application of power to the X80120 activates a Power On
Reset circuit that pulls the RESET pin active. This signal, if
used, prevents the system microprocessor from starting to
operate while there is insufficient voltage on any of the
supplies. This circuit also does the following:
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
• It prevents communication to the EEPROM during
unstable power conditions, greatly reducing the likelihood
of data corruption on power up.
• It allows time for all supplies to turn on and stabilize prior
to system initialization.
The POR/RESET circuit is activated when all voltages are
within specified ranges and the V1GDO and V4GDO time-
out conditions are met. The POR/RESET circuit will then
wait t_SPOR and de-assert the RESET pin. The POR delay
may be changed by setting the TPOR bits in register CR2.
The delay can be set to 100ms, 500ms, 1 second, or 5
seconds.
TABLE 1. POR RESET DELAY OPTIONS
TPOR1 TPOR0
t_SPOR DELAY BEFORE RESET
ASSERTION
0
0
100 miliseconds (default)
0
1
500 miliseconds
1
0
1 second
1
1
5 seconds
8
FN8151.0
January 20, 2005