X80120 Datasheet, PDF (6/17 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Dual Programmable Time Delay with Local/Remote Voltage Monitors

X80120, X80121
Serial Interface (Continued)Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC CHARACTERISTICS
f_SCL
t_IN
SCL Clock Frequency
Pulse width Suppression Time at
inputs
400
kHz
50
ns
t_AA (Note 1) SCL LOW to SDA Data Out Valid
t_BUF
Time the bus is free before start of new
(Note 1) transmission
0.1
1.5
µs
1.3
µs
t_LOW
Clock LOW Time
t_HIGH Clock HIGH Time
t_SU:STA Start Condition Setup Time
t_HD:STA Start Condition Hold Time
t_SU:DAT Data In Setup Time
t_HD:DAT Data In Hold Time
t_SU:STO Stop Condition Setup Time
t_DH (Note 1) Data Output Hold Time
t_R (Note 1) SDA and SCL Rise Time
t_F (Note 1) SDA and SCL Fall Time
t_SU:WP WP Setup Time
t_HD:WP WP Hold Time
t_SU:ADR A0, A1 Setup Time
t_HD:ADR A0, A1 Hold Time
t_SU:VP V_P Setup Time
Cb (Note 3) Capacitive load for each bus line
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb
20 +.1Cb
0.6
0
0.6
0
0.6
µs
µs
µs
µs
ns
µs
µs
ns
300
ns
300
ns
µs
µs
µs
µs
µs
400
pF
t_WC (Note 2) EEPROM Write Cycle Time
5
10
ms
NOTES:
1. This parameter is based on characterization data.
2. t_WC is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the
minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
3. This parameter is not 100% tested.
Timing Diagrams
t_BUF
SCL
t_SU:STA
SDA IN
SDA OUT
t_F
t_SU:DAT
t_HD:STA
t_HIGH
t_LOW
t_R
t_HD:DAT
t_SU:STO
t_AA t_DH
FIGURE 4. BUS TIMING
t_BUF
t_HD:STO
t_HD:DAT
6
FN8151.0
January 20, 2005