X80120 Datasheet, PDF (7/17 Pages) Intersil Corporation – Voltage Supervisor/Sequencer Dual Programmable Time Delay with Local/Remote Voltage Monitors

X80120, X80121
SCL
SDA IN
WWP
A1, A0
V_P
START
t_SU:WP
Clk 1
Slave Address Byte
Clk 9
t_HD:WP
t_SU:ADR
t_HD:ADR
t_SU:VP
FIGURE 5. WP, A0, A1, V_P PIN TIMING
STOP
t_WC
SCL
SDA
8^th Bit of Last Byte
ACK
t_WC
Stop
Condition
Start
Condition
FIGURE 6. WRITE CYCLE TIMING
Symbol Table
WAVEFORM INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Pin Configuration
X80120/21
V4GDO
V4MON
DNC
V_CC
DNC
20 19 18 17 16
1
15
2
14
3 ^{(5mm x 5mm)} ₁₃
4
12
5
11
6 7 8 9 10
WP
RESET
V1GDO
V1MON
SCL
7
FN8151.0
January 20, 2005