ISL78210 Datasheet, PDF (8/17 Pages) Intersil Corporation – Automotive PWM DC/DC Voltage Controller

ISL78210
Figure 5 shows the overcurrent set circuit. The inductor
consists of inductance L and the DC resistance DCR. The
inductor DC current I_L creates a voltage drop across
DCR, which is given by Equation 5:
V_DCR = I_L ⋅ DCR
(EQ. 5)
The I_OCSET current source sinks 10µA into the OCSET
pin, creating a DC voltage drop across the resistor
R_OCSET, which is given by Equation 6:
V_ROCSET = 10μA ⋅ R_OCSET
(EQ. 6)
The DC voltage difference between the OCSET pin and
the VO pin, which is given by Equation 7:
V_OCSET– V_VO = V_DCR– V_ROCSET =I_L ⋅DCR – I_OCSET⋅ R_OCSET
(EQ. 7)
The IC monitors the voltage of the OCSET pin and the VO
pin. When the voltage of the OCSET pin is higher than
the voltage of the VO pin for more than 10µs, an OCP
fault latches the converter off.
Component Selection For R_OCSET and C_SEN
The value of R_OCSET is calculated with Equation 8 which
is written as follows:
R_OCSET
=
I_{--O-----C-----}⋅_---D_-----C_-----R_---
I_OCSET
(EQ. 8)
Where:
- R_OCSET (Ω) is the resistor used to program the
overcurrent setpoint
- I_OC is the output DC load current that will activate
the OCP fault detection circuit
- DCR is the inductor DC resistance
For example, if I_OC is 20A and DCR is 4.5mΩ, the choice
of R_OCSET is = 20Ax4.5mΩ/10µA = 9kΩ.
Resistor R_OCSET and capacitor C_SEN form an R-C
network to sense the inductor current. To sense the
inductor current correctly not only in DC operation, but
also during dynamic operation, the R-C network time
constant R_OCSET C_SEN needs to match the inductor time
constant L/DCR. The value of C_SEN is then written as
follows:
C_SEN = -_R----_O-----_C----_S----_E--^L--_T----_â‹---_D-----_C-----_R---
(EQ. 9)
For example, if L is 1.5µH, DCR is 4.5mΩ, and R_OCSET is
9kΩ, the choice of C_SEN = 1.5µH/(9kΩx4.5mΩ) =
0.037µF.
When an OCP fault is declared, the PGOOD pin will
pull-down to 35Ω and latch off the converter. The fault
will remain latched until the EN pin has been pulled below
the falling EN threshold voltage V_ENTHF or if VCC has
decayed below the falling POR threshold voltage
V_{VCC_THF}
Overvoltage
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold V_OVRTH
for more than 2µs. For example, if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to rise above the typical V_OVRTH threshold of
116% for more than 2µs in order to trip the OVP fault
latch. In numerical terms, that would be
116% x 1.0V = 1.16V. When an OVP fault is declared,
the PGOOD pin will pull-down to 65Ω and latch-off the
converter. The OVP fault will remain latched until VCC
has decayed below the falling POR threshold voltage
V_{VCC_THF. An OVP fault cannot be reset by pulling the}
EN pin below the falling EN threshold voltage V_ENTHF.
Although the converter has latched-off in response to an
OVP fault, the LGATE gate-driver output will retain the
ability to toggle the low-side MOSFET on and off, in
response to the output voltage transversing the V_OVRTH
and V_OVFTH thresholds. The LGATE gate-driver will
turn-on the low-side MOSFET to discharge the output
voltage, protecting the load. The LGATE gate-driver will
turn-off the low-side MOSFET once the FB pin voltage is
lower than the falling overvoltage threshold V_OVRTH for
more than 2µs. The falling overvoltage threshold
V_OVFTH is typically 102%. That means if the FB pin
voltage falls below 102% x 1.0V = 1.02V, for more than
2µs, the LGATE gate-driver will turn off the low-side
MOSFET. If the output voltage rises again, the LGATE
driver will again turn on the low-side MOSFET when the
FB pin voltage is above the rising overvoltage threshold
V_OVRTH for more than 2µs. By doing so, the IC protects
the load when there is a consistent overvoltage
condition.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V_UVTH for
more than 2µs. For example, if the converter is
programmed to regulate 1.0V at the FB pin, that voltage
would have to fall below the typical V_UVTH threshold of
84% for more than 2µs in order to trip the UVP fault
latch. In numerical terms, that would be
84% x 1.0V = 0.84V. When a UVP fault is declared, the
PGOOD pin will pull-down to 95Ω and latch-off the
converter. The fault will remain latched until the EN pin
has been pulled below the falling EN threshold voltage
V_ENTHF or if VCC
threshold voltage
has decayed
V_{VCC_THF.}
below
the
falling
POR
Over-Temperature
When the temperature of the IC increases above the
rising threshold temperature T_OTRTH, it will enter the
OTP state that suspends the PWM, forcing the LGATE and
UGATE gate-driver outputs low. The status of the PGOOD
pin does not change nor does the converter latch-off. The
PWM remains suspended until the IC temperature falls
below the hysteresis temperature T_OTHYS, at which time
normal PWM operation resumes. The OTP state can be
reset if the EN pin is pulled below the falling EN threshold
voltage V_ENTHF or if VCC has decayed below the falling
POR threshold voltage ^V_{VCC_THF}. All other protection
circuits remain functional while the IC is in the OTP state.
It is likely that the IC will detect an UVP fault because in
the absence of PWM, the output voltage decays below
the undervoltage threshold V_UVTH.
8
FN7583.0
March 8, 2010