ISL78210 Datasheet, PDF (14/17 Pages) Intersil Corporation – Automotive PWM DC/DC Voltage Controller

ISL78210
OCSET AND VO PINS
The current-sensing network consisting of R_OCSET, R_O,
and C_SEN needs to be connected to the inductor pads for
accurate measurement of the DCR voltage drop. These
components however, should be located physically close
to the OCSET and VO pins with traces leading back to the
inductor. It is critical that the traces are shielded by the
ground plane layer all the way to the inductor pads. The
procedure is the same for resistive current sense.
FB AND SREF PINS
The input impedance of these pins is high, making it
critical to place the loop compensation components,
feedback voltage divider resistors, and C_SOFT capacitor
close to the IC, keeping the length of the traces short.
Typical Performance
100
95 ^{VIN = 8V}
90
85
V_IN = 12.6V
80
V_IN = 19V
75
70
65
60
55
50
0 2 4 6 8 10 12 14 16 18 20
I_OUT (A)
FIGURE 13. EFFICIENCY AT V_OUT = 1.1V
1.0
0.8
0.6
V_IN = 12.6V
0.4
0.2
0.0
-0.2
-0.4
V_IN = 8V
V_IN = 19V
-0.6
-0.8
-1.0
0 2 4 6 8 10 12 14 16 18 20
I_OUT (A)
FIGURE 15. SWITCHING FREQUENCY AT V_OUT = 1.1V
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are high dv/dt and
high di/dt, with high peak charging and discharging
current. The PGND pin can only flow current from the
gate-source charge of the low-side MOSFETs when LGATE
goes low. Ideally, route the trace from the LGATE pin in
parallel with the trace from the PGND pin; route the trace
from the UGATE pin in parallel with the trace from the
PHASE pin, and route the trace from the BOOT pin in
parallel with the trace from the PHASE pin. These pairs of
traces should be short, wide, and away from other traces
with high input impedance; weak signal traces should not
be in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It
is best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of
the application. An MLCC should be connected directly
across the drain of the upper MOSFET and the source of
the lower MOSFET to suppress the turn-off voltage spike.
1.0
0.8
0.6
0.4
V_IN = 19V
0.2
0.0
-0.2
-0.4
V_IN = 12.6V
V_IN = 8V
-0.6
-0.8
-1.0
0 2 4 6 8 10 12 14 16 18 20
I_OUT (A)
FIGURE 14. LOAD REGULATION AT V_OUT = 1.1V
EN
SREF
VOUT
PGOOD
FIGURE 16. START-UP, V_IN = 12.6V, V_OUT = 1.05V,
LOAD = 10A
14
FN7583.0
March 8, 2010