ISL6617A_14 Datasheet, PDF (8/15 Pages) Intersil Corporation – PWM Doubler with Output Monitoring Feature

ISL6617A
Timing Diagram
3.3V
PWMIN
1.7V
t_PDH
t_R1
PWMA/B _10%
90%
t_PDL
5V
90%
10%
t_F1
t_TSSHD
15ns
t_TSSHD
t_PTS
t_R2 ^90%
10%
FIGURE 1. TIMING DIAGRAM
t_F2
60%
t_PTS
Operation
Designed for high phase count and phase shedding applications,
the ISL6617A driverless phase doubler is meant to double or
quadruple (cascaded with two ISL6617s) the number of phases
that 3.3V multiphase controllers can support.
A rising transition on PWMIN initiates the turn-on of the PWMA/B
(see Figure 1). After a short propagation delay [t_PDH], the
PWMA/B begins to rise. Typical rise times [t_R1] are provided in
the “Electrical Specifications” table on page 7.
A falling transition on PWMIN indicates the turn-off of the
PWMA/B. The PWMA/B begins to fall [t_F1] after a propagation
delay [t_PDL], which is modulated by the current balance circuits.
When the PWMIN stays in the tri-state window for longer than
[t_TSSHD], both PWMA/B will pull to 40% of VCC so that the
cascaded 5V PWM input MOSFET driver or integrated power
stage can recognize tri-state.
EN_SYNC Operation
The EN_SYNC pin features multiple functions. It is the enable
input of the device and the input to select various operational
modes.
ENABLE OPERATION
maximum I_OUT current. This provides additional protection to the
load if the upper MOSFET experiences a short while the doubler
is enabled.
The EN_SYNC pin should remain high if driving the PWM line high
is prohibited for the associated controller. For proper system
interface, please refer to the respective device datasheet.
SYNCHRONOUS OPERATION
The ISL6617A can be set in interleaving mode or synchronous
mode by pulling the EN_SYNC pin to the respective level, as
shown in Table 1. A synchronous pulse can be sent to the phase
doubler during the load application to improve the voltage droop
and current balance while still maintaining interleaving operation
at DC load conditions. However, excessive ringback can occur;
hence, the synchronous mode operation should be carefully
investigated. Figure 3 shows how to generate a synchronous
pulse when a transient load is applied. The comparator should be
a fast comparator with a minimum delay.
20kΩ
2kΩ
COMP
49.9kΩ
+
-
1.0nF
VCC
0Ω
1kΩ
SYNC
DNP
EN_SYNC
PWMIN
PWMA/B
FIGURE 2. TYPICAL ENABLE OPERATION TIMING DIAGRAM
As shown in Figure 2, the ISL6617A disables the doubler
operation when the EN_SYNC pin is pulled to ground. When the
EN_SYNC returns high, the phase doubler will pull the PWM line
into the tri-state window, and then will be enabled only at the
leading edge of the PWM input. Prior to the first PWMIN rising
edge, both the PWMA and PWMB output will remain in tri-state
unless an overvoltage fault is detected. This fault is defined as
when a phase is detected to have more than 60% of the
FIGURE 3. TYPICAL SYNC PULSE GENERATOR
VARIOUS OPERATIONAL MODES
The ISL6617A has three distinct operating modes depending
upon the voltage level of the EN_SYNC pin. To ensure that the
ISL6617A is in operation, the pin must be above 2V. When the
EN_SYNC pin is set to above 97% of V_CC, the ISL6617A will
operate in interleaving mode with a maximum extension of 70ns.
When V_CC is between 78% and 85% of V_CC, the ISL6617A
operates in interleaving mode with a fixed extension of 120ns
and a variable extension of up to 70ns. This results in a minimum
extension of 120ns and a max of 190ns. To enter this 2nd
interleaving mode, the pin must remain in the 78% to 85% range
for at least 4 cycles. Between 54% and 64% of V_CC, the device
operates in synchronous mode. Figures 4 and 5 show simplified
synchronous and interleaving modes’ operational waveforms,
respectively.
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8
FN7844.0
December 19, 2014