ISL6617A_14 Datasheet, PDF (3/15 Pages) Intersil Corporation – PWM Doubler with Output Monitoring Feature

Pin Configuration
ISL6617A
ISL6617A
(10 LD DFN)
TOP VIEW
CSRTNA 1
CSENA 2
PWMIN 3
CSRTNB 4
CSENB 5
11
GND
10 PWMA
9 VCC
8 IOUT
7 EN_SYNC
6 PWMB
Functional Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
PIN SYMBOL
FUNCTION
CSRTNA
Output of the differential amplifier for Channel A. Connect a resistor on this pin to the negative rail of the sensed voltage to
set the current gain.
CSENA
Input of the differential amplifier for Channel A. Typically, the positive rail of sensed voltage via DCR sensing network
connects to this node.
PWMIN
The PWM input signal (3.3V) triggers the J-K flip flop and alternates its input to Channel A and B. Both channels are
effectively modulated. The PWM signal can enter three distinct states during operation; see “Operation” on page 8 for
further details. Connect this pin to the PWM output of the controller.
CSRTNB
Output of the differential amplifier for Channel B. Connect a resistor on this pin to the negative rail of the sensed voltage to
set the current gain.
CSENB
Input of the differential amplifier for Channel B. Typically, the positive rail of sensed voltage via DCR sensing network
connects to this node.
PWMB
PWM output of Channel B with 5V PWM tri-state compatibility.
EN_SYNC Driver Enable and Mode Selection Input. See “EN_SYNC Operation” on page 8 for more details.
IOUT
Current monitoring Output. It sources out the average current of both Channel A and B.
VCC
Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR ceramic
capacitor from this pin to GND.
PWMA
PWM output of Channel A with 5V PWM tri-state compatibility.
GND
Bias and reference ground. All signals are referenced to this node. Place a high quality low ESR ceramic capacitor from this
pin to VCC. Connect this pad to the power ground plane (GND) via thermally enhanced connection.
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FN7844.0
December 19, 2014