ISL6617A_14 Datasheet, PDF (12/15 Pages) Intersil Corporation – PWM Doubler with Output Monitoring Feature

ISL6617A
Current Balance and Current Monitoring
The sensed currents I_A and I_B from each respective channel are
summed together and divided by 2. The resulting average current
I_AVG provides a measure of the total load current. Channel
current balance is achieved by comparing the sensed current of
each channel to the average current to make an appropriate
adjustment to the PWMA and PWMB duty cycle with Intersil’s
patented current-balance method.
Channel current balance is essential in achieving the thermal
advantage of multiphase operation. With good current balance,
the power loss is equally dissipated over multiple devices and a
greater area.
The resulting average current I_AVG also goes out from the IOUT
pin for current monitoring and can also be fed back to the
controller’s ISEN lines for current balance, load-line regulation,
and overcurrent protection. For fast response to the current
information, the IOUT pin should have minimum decoupling; no
more than 50ns filter is recommended. The full scale of IOUT is
100µA; it typically should set resistor gain around 50µA to 80µA
at the full load to ensure that it will not hit the full scale prior to
the overcurrent trip point. At the same time, the current signal
accuracy is maximized.
Benefits of a High Phase Count System
At heavy load condition, efficiency can be improved by spreading
the load across many phases. This is primarily because the
resistive loss becomes the dominant component of total loss
budget at high current levels.
Since the load is carried by more phases, each power device
handles less current. In addition, the devices are likely to be
spread over a larger area on the Printed Circuit Board (PCB). Both
these factors result in improved heat dissipation for higher phase
count systems. By reducing the system’s operating temperature,
the reliability of the components is improved.
Furthermore, increasing the phase count also reduces the size of
ripple on both the input and output currents. It reduces EMI and
improves the efficiency. Figures 12 and 13 show the ripple
values for a 24-phase voltage regulator with the following
parameters:
• Input voltage: 12V
• Output voltage: 1.6V
• Duty cycle: 13.3%
• Load current: 200A
• Output Phase Inductor: 500nH
• Phase switching frequency: 200kHz
In this example, the 24-phase voltage regulator (VR) can run in
6-phase, 8-phase, 12-phase or 24-phase interleaving mode. In
6-phase interleaving mode, every 4 phases runs synchronously,
which yields 18.73A and 12.93A input and output ripple
currents, respectively. The 24-phase interleaving regulator
significantly drops these values to 4.05A and 0.78A, respectively.
As shown in Table 3, both input and output ripple currents are
reduced when more phases are running in interleaving mode.
Note that the 8-phase VR has lower output ripple current than the
12-phase VR since the 8-phase VR has better output ripple
cancellation factor close to the duty cycle of 1/8.
TABLE 3. RIPPLE CURRENT (UNIT: A)
INTERLEAVED PHASES
6
8
12 24
Input Ripple Current
18.73 11.64 8.79 4.05
Output Ripple Current
12.93 2.70 4.83 0.78
Figure 14 shows the efficiency of a 12-phase VR design, which
runs the doubler in interleaving and synchronous modes. For
comparison, a 6-phase VR with the same number of MOSFETs
and inductors is also plotted, clearly demonstrating the efficiency
improvement of a high-phase count system and interleaving
mode over synchronous mode resulting from the better ripple
cancellation.
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FN7844.0
December 19, 2014