ISL6617A_14 Datasheet, PDF (10/15 Pages) Intersil Corporation – PWM Doubler with Output Monitoring Feature

ISL6617A
ISL6617/ISL6611A
PWMA ^PWM1A
VCC
EN_X
ISL6617A
PWMA
PWMA
PWMIN
IOUT
ISENA
PWM1B
PWMB
PHASE1A
PHASE1B
PWM1
CSENA
PWMIN
IOUT
PWMB
PWMB
ISENB
PWMA ^PWM1C
PHASE1C
VOUT
CSENB
PWMIN
IOUT
ISENA
PWMB ^PWM1D
PHASE1D
VCC
EN_X
ISENB
ISL6617/ISL6611A
FIGURE 8. CASCADED PHASE DOUBLER SIMPLIFIED DIAGRAM
The ISL6617A can further be cascaded with ISL6617 or
ISL6611A (phase doubler with integrated 5V drivers), as shown in
Figure 8. This can quadruple the number of phases each PWM
line can support. Figure 9 shows the operational waveforms of
the cascaded doublers. The PWMIN pin of ISL6617 or ISL6611A
will be pulled to VCC when it is disabled (EN_x = Low). To avoid
driving the PWM outputs of the 1st stage ISL6617A by the 2nd
stage’s PWMIN, the 2nd stage doubler’s enable input should
remain high, i.e, tied to VCC, as shown in Figure 8. Note that
ISL6617A cannot cascade with itself and its PWMIN will not be
pulled to VCC when EN_x is disabled (Low).
allowable duty cycle will be less than 25%. All of the maximum
allowable duty cycle numbers referenced assume that the PWM
controller can send out a 100% duty cycle pulse. In many cases,
this is not achievable because the controller needs time to reset
its internal sawtooth ramp or internal max duty limit. However,
the fixed 120ns extension of interleaving mode 2 helps recover
the typical 1% duty cycle loss associated with the ramp reset
time.
PWM1
PWMA
To operate each phase at the switching frequency of f_SW, the
operational frequency of the controller needs to be scaled
accordingly for different modes, as shown in Table 2.
TABLE 2. CONTROLLER FREQUENCY AND MAXIMUM DUTY CYCLE
PWM1A
PWM1B
ISL6617A MAXIMUM DUTY CYCLE
OPERATIONAL MODES F_CONTROLLER
PER PHASE
Interleaving
2 x f_SW
50%
Synchronous
f_SW
100%
Cascaded Interleaving 4 x f_SW
25%
When the doubler operates in interleaving mode, the PWM
controller frequency should be set at two times the desired
phase frequency (f_SW). Since the input PWM pulse is divided into
half to feed into each phase of the doubler, the operational duty
cycle of each phase should be less than 50%. In synchronous
mode, the PWM controller should be operated at the same
frequency as the desired phase frequency. In this mode, the
allowable duty cycle is up to 100%. For cascaded interleaving,
the controller switching frequency needs to be set at four times
the phase frequency. During cascaded operation, the maximum
PWMB
PWM1C
PWM1D
FIGURE 9. CASCADED DOUBLER OPERATIONAL WAVEFORMS
To properly compensate the system that uses phase doublers,
the effective system sawtooth to calculate the modulator gain
should factor in the duty cycle limitation (D_MAX) as Equation 1.
For instance, when using ISL6617A and ISL6617 in cascaded
interleaving mode, the effective sawtooth amplitude should be
scaled as 3V/22.5% = 13.33V.
V _{R A M P _EFFECTIVE}
=
V_{----R----A---M-----P-}
D_MAX
(EQ. 1)
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FN7844.0
December 19, 2014