ISL6567_07 Datasheet, PDF (8/26 Pages) Intersil Corporation – Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers

ISL6567
FB and COMP (Pins 6 and 5)
The internal error amplifier’s inverting input and output
respectively. These pins are connected to the external
network used to compensate the regulator’s feedback loop.
ISEN1, ISEN2 (Pins 17, 13)
These pins are used to close the current feedback loop and
set the overcurrent protection threshold. A resistor
connected between each of these pins and their
corresponding PHASE pins determine a certain current flow
magnitude during the lower MOSFET’s conduction interval.
The resulting currents established through these resistors
are used for channel current balancing and overcurrent
protection.
Use the following equation to select the proper R_ISEN
resistor:
R_ISEN
=
r_{---D----S----(--O----N-----)---}×_-----I_{--O----U----T--}
50 μ A
where:
r_DS(ON) = lower MOSFET drain-source ON resistance (Ω)
I_OUT = channel maximum output current (A)
Read ‘Current Loop’, ‘Current Sensing’, ‘Channel-Current
Balance’, and ‘Overcurrent Protection’ paragraphs for more
information.
UGATE1, UGATE2 (Pins 19, 11)
Connect these pins to the upper MOSFETs’ gates. These
pins are used to control the upper MOSFETs and are
monitored for shoot-through prevention purposes. Minimize
the impedance of these connections. Maximum individual
channel duty cycle is limited to 66%.
BOOT1, BOOT2 (Pins 20, 10)
These pins provide the bias voltage for the upper MOSFETs’
drives. Connect these pins to appropriately-chosen external
bootstrap capacitors. Internal bootstrap diodes connected to
the PVCC pins provide the necessary bootstrap charge.
Minimize the impedance of these connections.
PHASE1, PHASE2 (Pins 18, 12)
Connect these pins to the sources of the upper MOSFETs.
These pins are the return path for the upper MOSFETs’
drives. Minimize the impedance of these connections.
LGATE1, LGATE2 (Pins 16, 14)
These pins are used to control the lower MOSFETs and are
monitored for shoot-through prevention purposes. Connect
these pins to the lower MOSFETs’ gates. Minimize the
impedance of these connections.
SS (Pin 23)
This pin allows adjustment of the output voltage soft-start
ramp rate, as well as the hiccup interval following an
overcurrent event. The potential at this pin is used as a clamp
voltage for the internal error amplifier’s non-inverting input,
regulating its rate of rise during start-up. Connect this pin to a
capacitor referenced to ground. Small internal current sources
linearly charge and discharge this capacitor, leading to similar
variation in the ramp up/down of the output voltage. While
below 0.3V, all output drives are turned off. As this pin ramps
up, the drives are not enabled but only after the first UGATE
pulse emerges (avoid draining the output, if pre-charged). If
no UGATE pulse are generated until the SS exceeds the top
of the oscillator ramp, at that time all gate operation is
enabled, allowing immediate draining of the output, as
necessary.
SS voltage has a ~0.7V offset above the reference clamp,
meaning the reference clamp rises from 0V with unity gain
correspondence as the SS pin exceeds 0.7V. For more
information, please refer to the Soft-Start paragraph.
FS (Pin 22)
This pin is used to set the switching frequency. Connect a
resistor, R_FS, from this pin to ground and size it according to
the graph in Figure 1 or the following equation:
R_FS
=
( 10.61
10
–
( 1.035
⋅
log
(
FS
W⁾⁾⁾
200k
100k
50k
20k
10k
100k
200k
500k
1M
2M
Switching Frequency (Hz)
FIGURE 1. SWITCHING FREQUENCY VS. R_FS VALUE
PGOOD (Pin 21)
This pin represents the output of the on-board power-good
monitor. Thus, the FB pin is monitored and compared against
a window centered around the available reference; an FB
voltage within the window disables the open-collector output,
allowing the external resistor to pull-up PGOOD high.
Approximate pull-down device impedance is 65Ω.
While operating with an external reference, the power-good
function is enabled once the MON pin amplitude exceeds its
monitored threshold (typically 300mV).
8
FN9243.2
March 20, 2007