ISL6567_07 Datasheet, PDF (20/26 Pages) Intersil Corporation – Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers

ISL6567
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
value for R2 for desired converter bandwidth (F₀). If
setting the output voltage via an offset resistor connected
to the FB pin, Ro in Figure 24, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier, in order to compensate for the
attenuation introduced by the resistor divider, the
R2
=
---^V----^O-----^S----^C-----^â‹---^R-----¹-----^â‹---^F----⁰----
d_MAX ⋅ V_IN ⋅ F_LC
obtained R2 value needs be multiplied by a factor of
(R_P+R_S)/R_P. The remainder of the calculations remain
unchanged, as long as the compensated R2 value is
used.
2. Calculate C1 such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F_CE/F_LC, the lower the F_Z1
frequency (to maximize phase boost at F_LC).
C1
=
-----------------------¹------------------------
2π ⋅ R2 ⋅ 0.5 ⋅ F_LC
3. Calculate C2 such that F_P1 is placed at F_CE.
C2
=
-------------------------^C-----¹---------------------------
2π ⋅ R2 ⋅ C1 ⋅ F_CE – 1
4. Calculate R3 such that F_Z2 is placed at F_LC. Calculate C3
such that F_P2 is placed below F_SW (typically, 0.5 to 1.0
times F_SW). F_SW represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F_P2 lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R3
=
--------^R----¹---------
F_{----S----W----}
F_LC
–
1
C3
=
------------------------¹-------------------------
2π ⋅ R3 ⋅ 0.7 ⋅ F_SW
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G_MOD), feedback
compensation (G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
⋅
--------------------------¹-----+-----^s----⁽--^f--⁾----^â‹---^E-----^â‹---^C-----------------------------
1 + s(f) ⋅ (E + D) ⋅ C + s²(f) ⋅ L ⋅ C
G_FB(f)
=
-----¹-----+-----^s---⁽---^f--⁾----^â‹---^R----²-----^â‹---^C-----¹-------
s(f) ⋅ R1 ⋅ (C1 + C2)
⋅
⋅ -------------------------------¹-----+-----^s---⁽--^f---⁾---^â‹---⁽---^R----¹-----+-----^R-----³----⁾---^â‹---^C-----³--------------------------------
(1
+
s(f)
⋅
R3
⋅
C3
)
⋅
⎛
⎝
1
+
s
(
f
)
⋅
R
2
⋅
⎛
⎝
C^-C----1^{-1----+-⋅---C-}C^----2-2^{--⎠⎞}
⎞
⎠
G_CL(f) = G_MOD(f) ⋅ G_FB(f)
where, s(f) = 2π ⋅ f ⋅ j
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
---------------¹----------------
2π ⋅ R2 ⋅ C1
F_P1
=
----------------------¹------------------------
2
π
⋅
R
2
⋅
-^C-----¹-----^â‹---^C-----²---
C1 + C2
F_Z2
=
-------------------------¹--------------------------
2π ⋅ (R1 + R3) ⋅ C3
F_P2
=
---------------¹----------------
2π ⋅ R3 ⋅ C3
Figure 25 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F_P2 against the capabilities of the error
amplifier. The closed loop gain, G_CL, is constructed on the
log-log graph of Figure 25 by adding the modulator gain,
G_MOD (in dB), to the feedback compensation gain, G_FB (in
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
20
log
⎛
⎝
RR-----21--_⎠⎞
0
20log -^d----^M-----^A-----^X-----^â‹----V----I--N---
V_OSC
G_FB
G_CL
LOG
F_LC F_CE F₀
G_MOD
FREQUENCY
FIGURE 25. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model presented
makes a number of approximations and is generally not
accurate at frequencies approaching or exceeding half the
switching frequency. When designing compensation networks,
select target crossover frequencies in the range of 10% to 30%
of the per-channel switching frequency, F_SW.
OUTPUT FILTER DESIGN
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the square
wave voltage at the phase nodes. Additionally, the output
capacitors must also provide the energy required by a fast
transient load during the short interval of time required by the
controller and power train to respond. Because it has a low
bandwidth compared to the switching frequency, the output
filter limits the system transient response leaving the output
capacitor bank to supply the load current or sink the inductor
20
FN9243.2
March 20, 2007