ISL6567_07 Datasheet, PDF (7/26 Pages) Intersil Corporation – Multipurpose Two-Phase Buck PWM Controller with Integrated MOSFET Drivers

ISL6567
Functional Pin Description
VCC (Pin 8)
Bias supply for the IC’s small-signal circuitry. Connect this
pin to a 5V supply and locally decouple using a quality 0.1μF
ceramic capacitor. This pin is monitored for POR purposes.
VCC bias may be applied in the absence of PVCC bias.
PVCC (Pin 15)
Power supply pin for the MOSFET drives. Connect this pin to
a 5V supply and locally decouple using a quality 1μF
ceramic capacitor. This pin is monitored for POR purposes.
PVCC bias should not be applied in the absence of VCC
bias.
VREG (Pin 7)
This pin is the output of the internal shunt regulator. The
internal shunt regulator monitors and regulates the voltage
at the VCC pin. In applications where the chip bias, including
that necessary to drive the external MOSFETs, is below the
current rating of this pin, connect it to VCC and PVCC, then
connect this node to the input supply via a properly sized
resistor. Should the input voltage vary over a wide range
and/or the bias current required exceed the intrinsic
capability of the on-board regulator, use this pin in
conjunction with an external NPN transistor and a couple of
resistors to create a more flexible bias supply for the
ISL6567. In any configuration, pay particular attention to the
chip’s limitations in terms of both current sinking capability of
the shunt regulator, as well as the internal power dissipation.
For more information, refer to the Bias Supply
Considerations paragraph.
GND (Pin 25)
Connect this pad to the circuit ground using the shortest
possible path (one to four vias to the internal ground plane,
placed on the soldering pad are recommended). All internal
small-signal circuitry, as well as the lower gates’ return paths
are referenced to this pin.
REFTRK (Pin 24)
This pin represents an optional reference input, as well as a
clamp voltage for the internal reference. If utilizing the
ISL6567’s internal 0.6V reference, and desire no special
tracking features enabled, electrically connect this pin to the
VCC pin, or leave it open. Internal or external reference
operation mode is dictated by the MON pin.
While operating in internal reference mode, this pin
represents an internal reference clamp that can be used for
implementation of various tracking features. In this operating
mode, a small internal current is sourced on this pin, pulling it
high if left open.
If utilizing the ISL6567 in conjunction with an external
reference, connect the desired stimulus to this pin; the sensed
output of the ISL6567 converter follows this input.
While operating with an external reference, the power-good
and overvoltage protection functions are disabled while the
MON pin voltage is below its threshold (typically 300mV).
MON (Pin 3)
The status of this pin is checked every time the chip is
enabled or POR is released; should its potential be lower than
3.5V (typical), the REFTRK potential is assumed to be an
externally-provided reference and the ISL6567 proceeds to
regulate the sensed output voltage to this external reference.
When operating using the internal reference voltage, connect
this pin to VCC (to bypass the mechanism described above).
While operating with an externally-provided reference,
connect this pin to a properly-sized resistor divider off the
voltage to be monitored. PGOOD and OVP functions are
enabled when this pin exceeds its monitored threshold
(typically 300mV).
This pin is normally floating (high impedance input) until it
exceeds its detect threshold. Once the threshold is
exceeded, a small current is sourced on this pin; this current,
along with a properly sized resistor network, allows the user
to adjust the threshold hysteresis.
For more information, refer to the External Reference
Operation paragraph.
EN (Pin 9)
This pin is a precision-threshold (approximately 0.6V) enable
pin. Pulled above the threshold, the pin enables the controller
for operation, initiating a soft-start. Normally a high impedance
input, once it is pulled above its threshold, a small current is
sourced on this pin; this current, along with a properly sized
resistor network, allows the user to adjust the threshold
hysteresis. Pulled below the falling threshold, this pin disables
controller operation, by ramping down the SS voltage and
discharging the output.
VSEN, RGND, and VDIFF (Pins 2, 1, and 4)
The inputs and output of the on-board unity-gain operational
amplifier intended for differential output sensing. Connect
RGND and VSEN to the output load’s local GND and VOUT,
respectively; VDIFF will reflect the load voltage referenced to
the chip’s local ground. Connect the feedback network to the
voltage thus reflected at the VDIFF pin. Should the circuit not
allow implementation of remote sensing, connect the VSEN
and RGND pins to the physical place where voltage is to be
regulated.
Connect the resistor divider setting the output voltage at the
input of the differential amplifier. To minimize the error
introduced by the resistance of differential amplifier’s inputs,
select resistor divider values smaller than 1kΩ. VDIFF is
monitored for overvoltage events and for PGOOD reporting
purposes.
7
FN9243.2
March 20, 2007