ISL6539 Datasheet, PDF (8/20 Pages) Intersil Corporation – Wide Input Range Dual PWM Controller with DDR Option

Block Diagram
BOOT1
UGATE1
PHASE1
PGND1
LGATE1
VCC
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
VSEN1
300kΩ
500kΩ
-
+
+ _0.9V
REF
SOFT1
1MΩ
16.7pF
1.25pF
4.4kΩ
ERROR AMP 1
ISEN1 140Ω
CURRENT
SAMPLE
OCSET1
-
+
CURRENT
SAMPLE
+ ^{0.9V REFERENCE}
1/2.9
OCSET1
1/33.1
ISEN1
PG1 EN1
VCC GND
EN2
REF/PG2
DDR = 0
DDR = 1
OV UV
PGOOD
POR
ENABLE
BIAS SUPPLIES
REFERENCE
FAULT LATCH
SOFT-START
DDR MODE
CONTROL
OV UV
PGOOD
-
PWM1
+
OC1 DDR OC2
PWM2
-
+
DUTY CYCLE RAMP GENERATOR
PWM CHANNEL PHASE CONTROL
DDR EN1 EN2
VIN
CH1 CH2 φ
0
1
1 5V Ù 15.0V
180°
1
1
1
V_IN = 5V
90°
V_IN = GND
0°
-
OC1
+
VIN
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
DDR
VCC
OC2
-
+
SAME STATE FOR
8 CLOCK CYCLES
REQUIRED TO LATCH
OVERCURRENT FAULT
ADAPTIVE DEAD-TIME
DIODE EMULATION
V/I SAMPLE TIMING
BOOT2
UGATE2
PHASE2
PGND2
LGATE2
VCC
16.7pF
1MΩ
4.4kΩ
1.25pF
ERROR AMP 2
500kΩ
-
+
300kΩ
(200kΩ, DDR = 1)
VSEN2
SOFT2
-
CURRENT
+
SAMPLE
0.9V REFERENCE ₊
DDR = 0
+
0.9V
REF
DDR = 1
140Ω ISEN2
CURRENT
SAMPLE
DDR = 0OCSET2
DDR = 1
1/33.1
ISEN2
+
-
DDR VREF
BUFFER AMP
1/2.9
OCSET2
+
-
DDR VTT
REFERENCE