ISL6539 Datasheet, PDF (6/20 Pages) Intersil Corporation – Wide Input Range Dual PWM Controller with DDR Option

ISL6539
capacitor with the cathode of the bootstrap diode. The anode
of the bootstrap diode is connected to the VCC voltage.
ISEN1, ISEN2 (Pin 7, 22)
These pins are used to monitor the voltage drop across the
lower MOSFET for current feedback and overcurrent
protection. For precise current detection these inputs can be
connected to the optional current sense resistors placed in
series with the source of the lower MOSFETs.
EN1, EN2 (Pin 8, 21)
These pins enable operation of the respective converter
when high. When both pins are low, the chip is disabled and
only low leakage current is taken from VCC and VIN. EN1
and EN2 can be used independently to enable either
Channel 1 or Channel 2, respectively.
VSEN1, VSEN2 (Pin 10, 19)
These pins are connected to the resistive dividers that set
the desired output voltage. The PGOOD, UVP, and OVP
circuits use this signal to report output voltage status.
OCSET1 (Pin 11)
This pin is a buffered 0.9V internal reference voltage. A
resistor from this pin to ground sets the overcurrent
threshold for the first controller.
SOFT1, SOFT2 (Pin 12, 17)
These pins provide soft-start function for their respective
controllers. When the chip is enabled, the regulated 5µA
pull-up current source charges the capacitor connected from
the pin to ground. The output voltage of the converter follows
the ramping voltage on the SOFT pin in the soft-start
process with the SOFT pin voltage as reference. When the
SOFT pin voltage is higher than 0.9V, the error amplifier will
use the internal 0.9V reference to regulate output voltage.
In the event of undervoltage and overcurrent shutdown, the
soft-start pin is pulled down through a 2kΩ resistor to ground
to discharge the soft-start capacitor.
DDR (Pin 13)
When the DDR pin is low, the chip can be used as a dual
switcher controller. The output voltage of the two channels
can be programmed independently by VSENx pin resistor
dividers. The PWM signals of Channel 1 and Channel 2 will
be synchronized 180° out-of-phase.
When the DDR pin is high, the chip transforms into a
complete DDR memory solution. The OCSET2 pin becomes
an input through a resistor divider tracking to VDDQ/2. The
PG2/REF pin becomes the output of the VDDQ/2 buffered
voltage. The VDDQ/2 voltage is also used as the reference
to the error amplifier by the second channel. The channel
phase-shift synchronization is determined by the VIN pin
when DDR = 1 as described in VIN (Pin 14).
VIN (Pin 14)
This pin has multiple functions. When connected to the input
voltage, it provides a feed-forward input to the oscillator for
the rejection of input voltage variation. The ramp of the PWM
comparator is proportional to the voltage on this pin (see
Table 1 and Table 2 for details). While the DDR pin is high (in
the DDR application) and when the VIN pin voltage is tied to
5V, it commands 90° out-of-phase channel synchronization,
with the second channel lagging the first channel, to reduce
inter-channel interference. While the DDR pin is high (in the
DDR application) and when the VIN pin voltage is tied to
ground, it commands in-phase channel synchronization.
PG1 (Pin 15)
PGOOD1 is an open drain output used to indicate the status
of the output voltage. This pin is pulled low when the first
channel output is out of ±11% of the set value.
PG2/REF (Pin 16)
This pin has a double function, depending on the mode of
operation.
When the chip is used as a dual channel PWM controller
(DDR = 0), the pin provides an open drain PGOOD2
function for the second channel the same way as PG1. The
pin is pulled low when the second channel output is out of
±11% of the set value.
In DDR mode (DDR = 1), this pin is the output of the buffer
amplifier that takes VDDQ/2 voltage applied to OCSET2 pin
from the resistor divider. It can source a typical 10mA current.
OCSET2 (Pin 18)
In a dual channel application with DDR = 0, a resistor from
this pin to ground sets the overcurrent threshold for the
second channel controller. Its voltage is the buffered internal
0.9V reference.
In the DDR application with DDR = 1, this pin connects to the
center point of a resistor divider tracking the VDDQ/2. This
voltage is then buffered by an amplifier voltage follower and
sent to the PG2/REF pin. It sets the reference voltage of
Channel 2 for its regulation.
VCC (Pin 28)
VCC provides the bias supply for the ISL6539. The supply to
VCC should be locally bypassed using a ceramic capacitor.
Typical Application
Figures 3 and 4 show the application circuits of a dual
channel DC/DC converter.
The power supply in Figure 3 provides +V2.5 and +V1.8
voltages for memory and the graphics interface chipset from
a 5.0VDC to 15VDC input rail.
Figure 4 illustrates the application circuit for a DDR memory
power solution. The power supply shown in Figure 4
generates +2.5V VDDQ voltage. The +1.25V VTT
termination voltage tracks VDDQ/2 and is derived from
+2.5V VDDQ. To complete the DDR memory power
requirements, the +1.25V reference voltage is provided
through the PG2 pin. In this application circuit shown, two
output 220µF capacitors are used at the outputs.
6
FN9144.6
April 29, 2010