ISL6539 Datasheet, PDF (5/20 Pages) Intersil Corporation – Wide Input Range Dual PWM Controller with DDR Option

ISL6539
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
PWM CONVERTERS
Load Regulation
0.0mA < IVOUT1 <5.0A; 5.0V < VIN <15.0V
-2.0
VSEN Pin Bias Current
IVSEN (Note 3)
-
Minimum Duty Cycle
DMIN
-
Maximum Duty Cycle
DMAX
-
Undervoltage Shut-Down Level
VUVL Fraction of the set point; ~2µs noise filter
70
Overvoltage Protection
VOVP1 Fraction of the set point; ~2µs noise filter
110
GATE DRIVERS
Upper Drive Pull-Up Resistance
R2UGPUP VCC = 5V
-
Upper Drive Pull-Down Resistance
R2UGPDN VCC = 5V
-
Lower Drive Pull-Up Resistance
R2LGPUP VCC = 5V
-
Lower Drive Pull-Down Resistance
R2LGPDN VCC = 5V
-
POWER GOOD AND CONTROL FUNCTIONS
Power Good Lower Threshold
Power Good Higher Threshold
VPG_- Fraction of the set point; ~3µs noise filter
84
VPG+ Fraction of the set point; ~3µs noise filter.
110
PGOODx Leakage Current
IPGLKG VPULLUP = 5.5V
-
PGOODx Voltage Low
VPGOOD IPGOOD = -4mA
-
ISEN Sourcing Current
(Note 3)
-
OCSET Sourcing Current Range
2
EN - Low (Off)
-
EN - High (On)
2.0
DDR - Low (Off)
-
DDR - High (On)
3
DDR REF Output Voltage
VDDREF DDR = 1, IREF = 0...10mA
0.99*
VOC2
DDR REF Output Current
IDDREF DDR = 1 (Note 3)
-
NOTES:
3. Limits should be considered typical and are not production tested.
TYP
-
80
4
87
75
115
4
2.3
4
1.1
89
115
-
0.5
-
-
-
-
-
-
VOC2
10
MAX
+2.0
-
-
-
80
-
8
4
8
3
92
120
1
1
260
20
0.8
-
0.8
-
1.01*
VOC2
12
UNITS
%
nA
%
%
%
%
Ω
Ω
Ω
Ω
%
%
µA
V
µA
µA
V
V
V
V
V
mA
Functional Pin Description
GND (Pin 1, 9, 20)
Signal ground for the IC. All three ground pins must be
connected to ground for proper IC operation. Connect to the
ground plane through a path as low in inductance as
possible.
LGATE1, LGATE2 (Pin 2, 27)
Connect these pins to the gates of the corresponding lower
MOSFETs. These pins provide the PWM-controlled gate
drive for the lower MOSFETs.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers, and are connected to sources of the lower
MOSFETs of their respective converters. These pins must
be connected to the ground plane through a path as low in
inductance as possible.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
UGATE1, UGATE2 (Pin 5, 24)
Connect these pins to the gates of the corresponding upper
MOSFETs. These pins provide the PWM-controlled gate
drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect these pins to the junction of the bootstrap
5
FN9144.6
April 29, 2010