ISL6539 Datasheet, PDF (11/20 Pages) Intersil Corporation – Wide Input Range Dual PWM Controller with DDR Option

ISL6539
TABLE 1. PWM COMPARATOR RAMP AMPLITUDE FOR
DUAL SWITCHER APPLICATION
VIN PIN CONNECTIONS
VRAMP
AMPLITUDE
Ch1 and Ch2 Input Voltage Input voltage > 4.2V
Input voltage < 4.2V
V_IN/8
1.25V
GND
1.25V
TABLE 2. PWM COMPARATOR RAMP VOLTAGE AMPLITUDE
FOR DDR APPLICATION
VIN PIN CONNECTION
VRAMP
AMPLITUDE
Ch1 Input Voltage
Input voltage > 4.2V
Input voltage < 4.2V
V_IN/8
1.25V
GND
1.25V
Ch2 Input voltage >4.2V
0.625V
GND
1.25V
The small signal transfer function from the error amplifier
output voltage V_c to the output voltage V_o can be written in
Equation 7:
G(s)
=
G_m
-----------------^R----^o------------------
R_i + DCR + R_o
⎛
⎝
----^s----
Wz
+
1_⎠⎞
---------------------------------------------------------
⎛
⎝
------^s------
Wp1
+
1_⎠⎞
⎝⎛ _W^------s-_p^---₂^--
+
1_⎠⎞
(EQ. 7)
The DC gain is derived by shorting the inductor and opening
the capacitor. There is one zero and two poles in this transfer
function.
The zero is related to ESR and the output capacitor.
The first pole is a low frequency pole associated with the
output capacitor and its charging resistors. The inductor can
be regarded as short. The second pole is the high frequency
pole related to the inductor. At high frequency the output cap
can be regarded as a short circuit. By approximation, the
poles and zero are inversely proportional to the time
constants, associated with inductor and capacitor, by
Equations 8, 9 and 10:
Wz
=
-----------¹------------
ESR*C_o
(EQ. 8)
Wp1 = ₍---_E----_S-----_R------+-----₍--_R-----_i--+-----_D-¹----_C-----_R-----₎---_|-_|---_R-----_o---₎--_*---_C-----_o-
(EQ. 9)
Wp2
=
R_{-----i---+-----}D_----C_-----R_------+-----E_----S_-----R_------|_-|_---R_----o-
L_o
(EQ. 10)
Since the current loop separates the LC resonant poles into
two distant poles, and ESR zero tends to cancel the high
frequency pole, the second order system behaves like a first
order system. This control method simplifies the design of
the internal compensator and makes it possible to
accommodate many applications having a wide range of
parameters. The schematic for the internal compensator is
shown in Figure 8.
1.25pF
500k
TO PWM
COMPARATOR
4.4k
ISEN
1M 16.7pF
-
Vc ⁺
300k
0.9V
VSEN
FIGURE 8. THE INTERNAL COMPENSATOR
Its transfer function can be written as Equation 11:
Gcomp(s)
=
1_----._-8_----5_---7_-----•_----1_----0_---⁵_{----⎝⎛--2}--------_π------^s--_f----_z------₁------+----1_{----⎠⎞---⎝⎛----2-------π}-----^s_{--f----z------2------+-----}1_{---⎠⎞-}
s
⎛
⎝
-------^s--------
2πf_p1
+
1_⎠⎞
(EQ. 11)
where:
f_z1 = 6.98kHz, f_z2 = 380kHz, and f_p1 = 137kHz
Outside the ISL6539 chip, a capacitor C_z can be placed in
parallel with the top resistor in the feedback resistor divider,
as shown in Figure 6. In this case the transfer function from
the output voltage to the middle point of the divider can be
written as:
Gfd(s)
=
-------^R-----²--------
R₁ + R₂
-_s---₍--_R---^s--₁--^R--_|--_|¹--_R--^C---₂-^z--₎--+-_C----_z¹----+-----₁--
(EQ. 12)
The ratio of R₁ and R₂ is determined by the output voltage
set point; therefore, the position of the pole and zero
frequency in Equation 12 may not be far apart; however,
they can improve the loop gain and phase margin with the
proper design.
The C_z can bring the high frequency transient output voltage
variation directly to the VSEN pin to cause the PGOOD drop.
Such an effect should be considered in the selection of C_z.
From the analysis in Equation 12, the system loop gain can
be written as Equation 13:
Gloop(s) = G(s) • Gcomp(s) • Gfd(s)
(EQ. 13)
Figure 9 shows the composition of the system loop gain. As
shown in the graph, the power stage became a well damped
second order system compared to the LC filter
characteristics. The ESR zero is so close to the high
frequency pole that they cancel each other out. The power
stage behaves like a first order system. With an internal
compensator, the loop gain transfer function has a cross
over frequency at about 30kHz. With a given set of
parameters, including the MOSFET r_DS(ON), current sense
11
FN9144.6
April 29, 2010