ISL6539 Datasheet, PDF (16/20 Pages) Intersil Corporation – Wide Input Range Dual PWM Controller with DDR Option

ISL6539
drop caused by the AC peak-to-peak current. These two
voltages can be represented by Equations 21 and 22:
ΔV_c
=
-----^I--^p---^p------
8Cf_sw
(EQ. 21)
ΔV_esr = I_{P – P}ESR
(EQ. 22)
These two components constitute a large portion of the total
output voltage ripple. Several capacitors have to be
paralleled in order to reduce the ESR and the voltage ripple.
If the output of the converter has to support another load
with high pulsating current, such as the first channel in
Figure 4, it feeds into the VTT channel which draws high
pulsating current. More capacitors are needed in order to
reduce the equivalent ESR and suppress the voltage ripple
to a tolerable level.
To support a load transient that is faster than the switching
frequency, more capacitors have to be used to reduce the
voltage excursion during load step change. Another aspect
of the capacitor selection is that the total AC current going
through the capacitors has to be less than the rated RMS
current specified on the capacitors, to prevent the capacitor
from overheating.
For DDR applications, as the second channel draws pulsate
current directly from the first channel, it is recommended to
parallel capacitors for output of the first channel to reduce
ESR and smooth ripple. Excessive high ripple voltage at the
output can propagate into the output of the error amplifier
and cause too much phase voltage jitter.
Input Capacitor Selection
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through Equation 23:
ICin_(RMS) =
IO
U
2
T
⋅
(D
–
D2
)
+
IRip
p
l
e(
p
–
2
p)
⋅
--^D----
12
(EQ. 23)
In addition to the bulk capacitance, some low ESL ceramic
decoupling is recommended to be used between the drain
terminal of the upper MOSFET and the source terminal of
the lower MOSFET, in order to clamp the parasitic voltage
ringing at the phase node in switching.
Choosing MOSFETs
For a maximum input voltage of 15V, at least a minimum 30V
MOSFETs should be used. The design has to trade off the
gate charge with the r_DS(ON) of the MOSFET:
• For the lower MOSFET, before it is turned on, the body
diode has been conducting. The lower MOSFET driver will
not charge the miller capacitor of this MOSFET.
• In the turning off process of the lower MOSFET, the load
current will shift to the body diode first. The high dv/dt of
the phase node voltage will charge the miller capacitor
through the lower MOSFET driver sinking current path.
This results in much less switching loss of the lower
MOSFETs.
The duty cycle is often very small in high battery voltage
applications, and the lower MOSFET will conduct most of
the switching cycle; therefore, the lower the r_DS(ON) of the
lower MOSFET, the less the power loss. The gate charge for
this MOSFET is usually of secondary consideration.
The upper MOSFET does not have this zero voltage
switching condition, and because the upper MOSFET
conducts for less time compared to the lower MOSFET, the
switching loss tends to be dominant. Priority should be given
to the MOSFETs with less gate charge, so that both the gate
driver loss, and switching loss, will be minimized.
For the lower MOSFET, its power loss can be assumed to be
the conduction loss only.
P_lower(V_IN) ≈ (1 – D(V_IN))I_load2r_DS(ON)Lower
(EQ. 24)
For the upper MOSFET, its conduction loss can be written as:
P_uppercond(V_IN) = D(V_IN)I_load2r_DS(ON)upper
(EQ. 25)
and its switching loss can be written as:
P_uppersw(V_IN) =
-^V----^I--^N----^I--^v---^a---^l--^l-^y---^t--^o----ⁿ---^f--^s---^w--
2
+
V_{-----I--N----}I_{--p---e---a----k---}t_--o---f--f--f_s---w----
2
(EQ. 26)
The peak and valley current of the inductor can be obtained
based on the inductor peak-to-peak current and the load
current. The turn-on and turn-off time can be estimated with
the given gate driver parameters in the “Electrical
Specifications” Table on page 4. For example, if the gate
driver turn-on path MOSFET has a typical ON-resistance of
4Ω, its maximum turn-on current is 1.2A with 5V V_CC. This
current would decay as the gate voltage increased. With the
assumption of linear current decay, the turn-on time of the
MOSFETs can be written as Equation 27:
t_on
=
--²---^Q-----^g----^d--
I_driver
(EQ. 27)
Q_gd is used because when the MOSFET drain-to-source
voltage has fallen to zero, it gets charged. Similarly, the
turn-off time can be estimated based on the gate charge and
the gate drivers sinking current capability.
16
FN9144.6
April 29, 2010