ISL6440A Datasheet, PDF (8/16 Pages) Intersil Corporation – Advanced PWM and Triple Linear Power Controller for Gateway Applications

ISL6440A
PGOOD
0V
SOFT-START
(1V/DIV)
0V
OUTPUT
VOLTAGES
(0.5V/DIV)
V_OUT2 (= 3.3V_IN)
V_OUT1 (DAC = 2.5V)
V_OUT4 (= 1.8V)
V_OUT3 (= 1.5V)
0V
T0 T1
T2
T3
T4
TIME
FIGURE 2. SOFT-START INTERVAL
The remaining outputs are also programmed to follow the
SS pin voltage. The PGOOD signal toggles ‘high’ when all
output voltage levels have exceeded their undervoltage
levels. The waveform for V_OUT2 represents the case where
SELECT is held ‘high’. The AGP bus voltage is controlled in
the same manner as the other linear regulators during the
soft-start sequence. Once the soft-start sequence is
complete (t4), the gate of the external pass device is fully
enhanced and V_OUT2 tracks the 3.3V_IN voltage. See the
Soft-Start Interval section under Applications Guidelines for
a procedure to determine the soft-start interval.
Fault Protection
All four outputs are monitored and protected against extreme
overload. A sustained overload on any output or an
overvoltage on V_OUT1 output (VSEN1) disables all outputs
and drives the FAULT/RT pin to VCC.
Figure 3 shows a simplified schematic of the fault logic. An
overvoltage detected on VSEN1 immediately sets the fault
latch. A sequence of three overcurrent fault signals also sets
the fault latch. The overcurrent latch is set dependent upon
the states of the overcurrent (OC), linear undervoltage (LUV)
and the soft-start signals. A window comparator monitors the
SS pin and indicates when C_SS is fully charged to 4V (UP
signal). An undervoltage on either linear output (VSEN2,
VSEN3, or VSEN4) is ignored until after the soft-start interval
(t4 in Figure 2). This allows V_OUT2 , V_OUT3, and V_OUT4 to
increase without fault at start-up. Cycling the bias input
voltage (+12V_IN on the VCC pin off, then on) resets the
counter and the fault latch.
LUV
OC1
0.15V +
-
SS
+
4V ^-
OV
OVER-
CURRENT
LATCH
SQ
INHIBIT
R
COUNTER
R
FAULT _VCC
LATCH
UP
SQ
POR
R
FAULT
FIGURE 3. FAULT LOGIC - SIMPLIFIED SCHEMATIC
Overvoltage Protection
During operation, a short on the upper MOSFET of the PWM
regulator (Q1) causes V_OUT1 to increase. When the output
exceeds the overvoltage threshold of 115% of DACOUT, the
overvoltage comparator trips to set the fault latch and turns
Q2 on. This blows the input fuse and reduces V_OUT1. The
fault latch raises the FAULT/RT pin to VCC.
A separate overvoltage circuit provides protection during the
initial application of power. For voltages on the VCC pin
below the POR (and above ~4V), the output level is
monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2 is driven on.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s
on-resistance, r_DS(ON) to monitor the current for protection
against shorted output. All linear controllers monitor their
respective VSEN pins for undervoltage events to protect
against excessive currents.
Figure 4 illustrates the overcurrent protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the inductor (L_OUT1). At time t1,
the OVERCURRENT comparator trips when the voltage
across Q1 (i_D • r_DS(ON)) exceeds the level programmed by
ROCSET. This inhibits all outputs, discharges the soft-start
capacitor (C_SS) with a 10mA current sink, and increments
the counter. C_SS recharges at t2 and initiates a soft-start
cycle with the error amplifiers clamped by soft-start. With
OUT1 still overloaded, the inductor current increases to trip
the overcurrent comparator. Again, this inhibits all outputs,
but the soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start
cycle repeats at t3 and trips the overcurrent comparator. The
SS pin voltage increases to 4V at t4 and the counter
increments to 3. This sets the fault latch to disable the
converter. The fault is reported on the FAULT/RT pin.
The linear controllers operate in the same way as the PWM
in response to overcurrent faults. The differentiating factor
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