ISL6440A Datasheet, PDF (12/16 Pages) Intersil Corporation – Advanced PWM and Triple Linear Power Controller for Gateway Applications

ISL6440A
R3, C1, C2, and C3) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick gain (R2/R1) for desired converter bandwidth
2. Place first zero below filter’s double pole (~75% F_LC)
3. Place second zero at filter’s double pole
4. Place first pole at the ESR zero
5. Place second pole at half the switching frequency
6. Check gain against error amplifier’s open-loop gain
7. Estimate phase margin - repeat if necessary
L_IN
+5V_IN
C_IN
+3.3V_IN
+12V
C_VCC
VCC GND
OCSET1
Q3
V_OUT2
DRIVE2
UGATE1
C_OUT2
PHASE1
V_OUT3
LGATE1
SS
C_SS
ISL6440A
C_OCSET1
R_OCSET1
Q1
L_OUT1
V_OUT1
C_OUT1
CR1
Q2
V_OUT4
C_OUT3
Q4
DRIVE3 DRIVE4
PGND
C_OUT4
Q5
+3.3V_IN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 8. Using the above guidelines
should yield a compensation gain similar to the curve plotted.
Check the compensation gain at F_P2 with the capabilities of the
error amplifier. The closed loop gain is constructed on the log-
log graph of Figure 9 by adding the modulator gain (in dB) to
the compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst-case component variations when
determining phase margin.
OSC
∆ V_OSC
PWM
COMP
-
+
V_IN
DRIVER
L_O
DRIVER
PHASE _CO
V_OUT
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C2
C1 _R2
Z_FB
V_OUT
Z_IN
C3 R3
R1
COMP
FB
-
+
ISL6440A
DACOUT
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Compensation Break Frequency Equations
F_Z1 = ₂----_π-----_×-----_R---¹--₂-----_×-----_C----₁--
F_Z2 = ₂----_π-----_×-----₍---_R----₁-----+-¹----_R-----₃---₎----_×-----_C-----₃-
F_P1
=
---------------------------¹---------------------------
2π
×
R
2
×


CC_-----11_-----×_+-----CC_----2_{-2--}
F_P2 = ₂----_π-----_×-----_R---¹--₃-----_×----_C-----₃--
F_Z1
F_Z2 F_P1 F_P2
OPEN LOOP
100
ERROR AMP GAIN
80
20
log



V-V----P-I--N-P---_{}
60
40
COMPENSATION
GAIN
20
0
-20
20
log


RR-----21--_
MODULATOR
-40
GAIN _{FLC FESR}
-60
10
100
1K
10K 100K
FREQUENCY (Hz)
CLOSED LOOP
GAIN
1M 10M
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
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