ISL6440A Datasheet, PDF (11/16 Pages) Intersil Corporation – Advanced PWM and Triple Linear Power Controller for Gateway Applications

ISL6440A
Shutdown
The ISL6440A features a dedicated shutdown pin (SD). A
TTL-compatible, logic high signal applied to this pin shuts
down (disables) all four outputs and discharges the soft-start
capacitor. Following a shutdown, a logic low signal
re-enables the outputs through initiation of a new soft-start
cycle. Left open this pin will asses a logic low state, due to its
internal pull-down resistor, thus enabling normal operation of
all outputs.
The PWM output does not switch until the soft-start voltage
(V_SS) exceeds the oscillator’s valley voltage. The references
on each linear’s error amplifier are clamped to the soft-start
voltage. Holding the SS pin low (with an open drain or
collector signal) turns off all four regulators.
The ‘11111’ VID code also shuts down the IC.
Layout Considerations
MOSFETs switch quickly and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn-
off transition of the upper PWM MOSFET. Prior to turn-off,
the upper MOSFET was carrying the full load current.
During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET or
Schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces minimize
the magnitude of voltage spikes. See Application Note
AN9836 for evaluation board drawings of the component
placement and the printed circuit board layout of a typical
application.
There are two sets of critical components in a DC-DC
converter using a ISL6440A controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate
equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.
The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high-
frequency ceramic decoupling capacitors, close to the power
switches. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.
The critical small signal components include the bypass
capacitor for VCC and the soft-start capacitor, C_SS . Locate
these components close to their connecting pins on the
control IC. Minimize any leakage current paths from SS
node, since the internal current source is only 28µA.
A multi-layer printed circuit board is recommended.
Figure 7 shows the connections of the critical components
in the converter. Note that the capacitors C_IN and C_OUT
each represent numerous physical capacitors. Dedicate
one solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dv/dt voltages,
the stray capacitor formed between these islands and the
surrounding circuitry will tend to couple switching noise.
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A peak
currents.
PWM Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.
Figure 8 highlights the voltage-mode control loop for a
synchronous rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage
(DACOUT). The error amplifier (Error Amp) output (V_E/A) is
compared with the oscillator (OSC) triangular wave to
provide a pulse-width modulated (PWM) wave with an
amplitude of V_IN at the PHASE node. The PWM wave is
smoothed by the output filter (L_O and C_O).
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A . This function is dominated by a DC
gain, given by V_IN/V_OSC, and shaped by the output filter,
with a double pole break frequency at F_LC and a zero
at F_ESR.
Modulator Break Frequency Equations
F_LC=
-------------------¹--------------------
2π × L_O × C_O
F_ESR= ₂----_π-----_×-----_E-----_S-¹---_R------_×-----_C----_O---
The compensation network consists of the error amplifier
(internal to the ISL6440A) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
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