ISL54302 Datasheet, PDF (8/16 Pages) Intersil Corporation – 12V, 1.5OHM Quad SPST Switch with Latched Parallel Interface

SW2-B
SW2-A
S2 CONTROL
ISL54302
S3 CONTROL
SW3-A
SW3-B
SW1-B
SW1-A
S1 CONTROL
INTERNAL
CS-LATCH
REGISTERS
INTERNAL
CS-LATCH
REGISTERS
S4 CONTROL
SW4-A
SW4-B
LEVEL
SHIFTER
LEVEL LEVEL
LEVEL LEVEL
SHIFTER SHIFTER SHIFTER SHIFTER
FIGURE 6. ISL54302 FUNCTIONAL DIAGRAM
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All switch contact
I/O pins contain ESD protection diodes from the pin to
VPLUS and to VSS (see Figure 7). To prevent forward
biasing these diodes, VPLUS, GND and VSS must be
applied before any input signals, and switch signal voltages
must remain between VPLUS and VSS. Digital control
signals should be limited to VLOGIC and VSS.
SPECIFIC POWER SEQUENCE
1. GND
2. VSS Typical . . . . . . . . . . . 3V to 0V with respect to GND
3. VPLUS Typical . . . . . . . +5V to +9V with respect to GND
4. VDD . . . . . . . . . . . . . . . . . . . +3V to with respect to VSS
5. VLOGIC . . . . . . . . . . . . . . . . . . +3V with respect to GND
If these conditions cannot be guaranteed, then one of the
following two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input. The resistor limits the input
current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
Adding a series resistor to the switch input defeats the purpose
of using a low r_ON switch, so two small signal diodes can be
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 7). These additional diodes
limit the analog signal from 1V below VPLUS to 1V above VSS.
The leakage current performance is unaffected by this
approach, but the switch resistance may increase, especially
at low supply voltages.
ESD Protection
The device contains ESD protection on the device pins.
These devices are design to work based on dV/dt. During
power-up, the user should review the rise/fall times on the
power connections. The rise time of the power rails should
not be faster than 1µs.
VPLUS
VDD
VLOGIC
VPLUS
CLAMP CLAMP CLAMP
VSS
VSS
GND
ONE FOR EACH PIN LISTED: 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B,
VDD, VLOGIC
VLOGIC
ONE FOR EACH PIN LISTED: S1-CTRL, S2-CTRL,
S3-CTRL, S4-CTRL, CS-LATCH
GND VSS
FIGURE 7. ESD/OVERVOLTAGE PROTECTION
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March 19, 2008