ISL54302 Datasheet, PDF (3/16 Pages) Intersil Corporation – 12V, 1.5OHM Quad SPST Switch with Latched Parallel Interface

ISL54302
Absolute Maximum Ratings
VPLUS to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to15V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
VLOGIC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5V
VSS to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4V to 0.3V
VPLUS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V
All Other Pins (Note 1) . . . . . . . . ((VSS) - 0.3V) to ((VPLUS) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 35mA
Peak Current, 1A-4A,1B-4B
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . 100mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>3kV
CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Thermal Information
Thermal Resistance (Typical)
θ_JA (°C/W) θ_JC (°C/W)
20 Ld QFN Package (Notes 2, 3) . . . . . .
32
1.4
Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Analog Switch Signal Range . . . . . . . . VSS + 0.5V to VPLUS - 0.5V
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on 1A-4A,1B-4B, exceeding VPLUS or VSS are clamped by internal diodes. DATA_IN, CLOCK_IN, CS_LATCH exceeding VLOGIC or
VSS are clamped by internal diodes. Limit forward diode current to maximum current ratings.
2. θ_JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Test Conditions: VPLUS = +9V, VSS = -3V Supply, VLOGIC = 3V, VDD = GND = 0V, V_INH = 2.2V, V_INL = 0.8V,
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP MIN
TYP
MAX
(°C) (Note 9) (Note 10) (Note 9) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-resistance, r_ON
I_COM = 10mA, VXA, VXB within analog signal
25
2.0
Ω
(see Figure 4)
Full
2.5
Ω
r_ON Matching Between Channels, I_COM = 10mA, VXA, VXB within analog signal range
25
0.2
Ω
Δr_ON
(Note 5)
Full
0.3
Ω
r_ON Flatness, r_FLAT(ON)
I_COM = 10mA, VXA, VXB within analog signal range
25
0.4
Ω
(Note 4)
Full
0.6
Ω
OFF Leakage Current, I_NO(OFF) VXA, VXB within analog signal range
25
15
nA
Full
-200
+200
nA
DIGITAL INPUT CHARACTERISTICS (Note 8)
Input Voltage High, Digital Interface SW-CTRL(1-4), CS_LATCH
Input Voltage Low, Digital Interface SW-CTRL(1-4), CS_LATCH
SW-CTRL (1-4) Into CS_Latch
Setup Time
t_SETUP (Note 6, Figure 5)
Full
2.2
1.75
V
Full
1.75
0.8
V
Full
1
ns
SW-CTRL (1-4) Into CS_Latch Hold t_HOLD (Note 6, Figure 5)
Time
Input Current, I_INH, I_INL
CS_LATCH Rise, Fall Time
V_IN = 0V or VLOGIC
10% to 90% and 90% to 10%
Full
3.5
ns
Full
-1
0.01
1
µA
Full
3
ns
CS_LATCH Minimum Pulse Width Rising to Falling Edge 50% Points
Full
10
ns
SWITCH DYNAMIC CHARACTERISTICS
Turn-ON Time, t_ON
VXA, VXB = 3V, R_L = 300Ω, C_L = 35pF, V_IN = 0V to 3V, 25
50
ns
(see Figure 1)
Full
55
ns
3
March 19, 2008