ISL54302 Datasheet, PDF (6/16 Pages) Intersil Corporation – 12V, 1.5OHM Quad SPST Switch with Latched Parallel Interface

ISL54302
Test Circuits and Waveforms
3V
CS-LATCH
INPUT
0V
50%
t_r < 20ns
t_f < 20ns
VPLUS
VDD
VLOGIC
C
C
C
C
V_NB
SWITCH
OUTPUT
V_NB
t_ON
V_OUT
t_OFF
25%
75%
V_OUT
Switch changes state on rising edge of CS-LATCH. V_NA = VOUT at
all times.
V_NB
SWITCH
INPUTS
1-4B
IN _LATCH
1-4A
GND
SX-CRTL
INPUT
C
VSS
V_OUT
R_L
300Ω
C_L
35pF
Repeat test for all switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V _(NB)
-----------^R-----^L------------
R_L + r_(ON)
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
VPLUS
VDD
VLOGIC
C
C
C
SWITCH
OUTPUT
V_OUT
ON
CONTROLLER
SEQUENCE
SW: ON/OFF/ON
ΔV_OUT
OFF
3V
ON
0V
Q = ΔV_OUT x C_L
R_G
1-4A
1-4B
LATCH
V_G
IN
GND
C
VSS
V_OUT
C_L
Switch changes state on rising edge of CS-LATCH.
FIGURE 2A. MEASUREMENT POINTS
Repeat test for all switches. C_L includes fixture and stray
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
SIGNAL
GENERATOR
VPLUS
VDD
VLOGIC
C
C
C
1-4A
CS-LATCH/SX-CRTL
ANALYZER
R_L
1-4B
Repeat test for all switches.
GND
C
VSS
FIGURE 3. OFF ISOLATION TEST CIRCUIT
6
VPLUS
VDD
VLOGIC
C
C
C
r_ON = V₁/10mA
V_XA
1-4A
10mA
V₁
CS-LATCH/SX-CRTL
1-4B
GND
Repeat test for all switches.
C
VSS
FIGURE 4. r_ON TEST CIRCUIT
March 19, 2008