ISL23348 Datasheet, PDF (8/19 Pages) Intersil Corporation – Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23348
Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 20) (Note 8) (Note 20) UNITS
t_SU:STO
t_HD:STO
t_DH
t_R
t_F
Cb
STOP Condition Set-up Time
From SCL rising edge crossing 70% of V_LOGIC, to
600
SDA rising edge crossing 30% of V_LOGIC
STOP Condition Hold Time for Read From SDA rising edge to SCL falling edge; both
or Write
crossing 70% of V_LOGIC
1300
Output Data Hold Time
From SCL falling edge crossing 30% of V_LOGIC,
0
until SDA enters the 30% to 70% of V_LOGIC
window. I_OL = 3mA, V_LOGIC > 2V. I_OL = 0.5mA,
V_LOGIC < 2V
SDA and SCL Rise Time
From 30% to 70% of V_LOGIC
20 + 0.1 x Cb
SDA and SCL Fall Time
From 70% to 30% of V_LOGIC
20 + 0.1 x Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
ns
ns
ns
250
ns
250
ns
400
pF
t_SU:A
A1, A0, A2 Setup Time
Before START condition
600
ns
t_HD:A
A1, A0, A2 Hold Time
After STOP condition
600
ns
NOTES:
8. Typical values are for T_A = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)₁₂₇ – V(RW)₀]/127. V(RW)₁₂₇ and V(RW)₀ are V(RW) for the DCP register set to 7f hex and 00 hex respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)₀/LSB.
11. FS error = [V(RW)₁₂₇ – V_CC]/LSB.
12. DNL = [V(RW)_i – V(RW)_i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
13. INL = [V(RW)_i – i • LSB – V(RW)₀]/LSB for i = 1 to 127
14.
TC_V
=
M_------a_----x_---(_--V_---V-(_--R_-(--R--W_--W---)_--i-i-)_{-(--+-–---2-}M_--5---i_-°-n_---C-(_---V_)--)-(_---R_----W_------)_--i--)
×
------¹----⁰----⁶-------
+ 165 °C
for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
and Min( ) is the minimum value of the wiper voltage over the temperature range.
15. MI = |RW₁₂₇ – RW₀|/127. MI is a minimum increment. RW₁₂₇ and RW₀ are the measured resistances for the DCP register set to 7f hex and 00
hex respectively.
16. Roffset = RW₀/MI, when measuring between RW and RL.
Roffset = RW₁₂₇/MI, when measuring between RW and RH.
17. RDNL = (RW_i – RW_i-1)/MI -1, for i = 8 to 127.
18. RINL = [RW_i – (MI • i) – RW₀]/MI, for i = 8 to 127.
19.
TC_R
=
[_---M_-----a_----x_-R--(_--R_-i--(--i+_--)_{--2-–--5---}M_-°----iC_--n_--)--(_--R_----i_--)_---]
×
------¹----⁰----⁶-------
+ 165 °C
for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
21. It is preferable to ramp up both the V_LOGIC and the V_CC supplies at the same time. If this is not possible, it is recommended to ramp-up the V_LOGIC
first followed by the V_CC.
22. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.
23. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.
8
FN7903.1
August 24, 2011