ISL23348 Datasheet, PDF (14/19 Pages) Intersil Corporation – Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23348
pins in order to initiate communication with the ISL23348. A
maximum of eight ISL23348 devices may occupy the I²C serial
bus (see Table 3).
V_LOGIC
Digital power source for the logic control section. It supplies an
internal level translator for 1.2V to 5.5V serial bus operation. Use
the same supply as the I²C logic source.
Principles of Operation
The ISL23348 is an integrated circuit incorporating four DCPs
with its associated registers and an I²C serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a
“make-before-break” mode when the wiper changes tap
positions.
Voltage at any of the DCP pins, RHi, RLi or RWi, should not
exceed V_CC level at any conditions during power-up and normal
operation.
The V_LOGIC pin is the
source. It should use
terminal for the logic control digital power
the same supply as the I²C logic source,
which allows reliable communication with a wide range of
microcontrollers and is independent from the V_CC level. This is
extremely important in systems where the master supply has
lower levels than the DCP analog supply.
DCP Description
Each DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are equivalent
to the fixed terminals of a mechanical potentiometer (RHi and RLi
pins). The RWi pin of the DCP is connected to intermediate nodes,
and is equivalent to the wiper terminal of a mechanical
potentiometer. The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of
a DCP contains all zeroes (WRi[7:0] = 00h), its wiper terminal (RW)
is closest to its “Low” terminal (RLi). When the WRi register of a DCP
contains all ones (WRi[7:0] = 7fh), its wiper terminal (RWi) is closest
to its “High” terminal (RHi). As the value of the WRi increases from
all zeroes (0) to all ones (127 decimal), the wiper moves
monotonically from the position closest to RLi to the position closest
to RHi. At the same time, the resistance between RWi and RLi
increases monotonically, while the resistance between RHi and RWi
decreases monotonically.
While the ISL23348 is being powered up, all the wipers (WRi) are
reset to 40h (64 decimal), which positions RWi at the center
between RLi and RHi.
The WRi can be read or written to directly using the I²C serial
interface as described in the following sections.
Memory Description
The ISL23348 contains five volatile 8-bit registers: Wiper Register
WR0, Wiper Register WR1, Wiper Register WR2, Wiper Register
WR3 and Access Control Register (ACR). The memory map of
ISL23348 is shown in Table 1. The Wiper Register WRi at address i
contains current wiper position of DCPi (i = 0, 1, 2, 3). The Access
Control Register (ACR) at address 10h contains information and
control bits described in Table 2.
ADDRESS
(hex)
10
3
2
1
0
TABLE 1. MEMORY MAP
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
ACR
40
WR3
40
WR2
40
WR1
40
WR0
40
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7
6
5
4
3
2
1
0
NAME/ 0 SHDN 0 0
0
0
0
0
VALUE
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., DCP is forced
to end-to-end open circuit and RW is connected to RL through a
2kΩ serial resistor, as shown in Figure 25. The default value of the
SHDN bit is 1.
RH
RW
2kΩ
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
When the device enters shutdown, all current DCP WRi settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WRi settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the
wipers will be RESET to their mid positions. This is done to avoid
an undefined state at the wiper outputs.
14
FN7903.1
August 24, 2011