ISL23348 Datasheet, PDF (2/19 Pages) Intersil Corporation – Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

Block Diagram
VLOGIC
SCL
SDA
A0
A1
A2
I/O
BLOCK
LEVEL
SHIFTER
Pin Configurations
ISL23348
(20 LD TSSOP)
TOP VIEW
RL0 1
RW0 2
V_CC 3
RH0 4
RL1 5
RW1 6
RH1 7
GND 8
V_LOGIC 9
A0 10
20 RL3
19 RW3
18 RH3
17 RL2
16 RW2
15 RH2
14 SCL
13 SDA
12 A2
11 A1
ISL23348
(20 LD QFN)
TOP VIEW
20 19 18 17
V_CC 1
RH0 2
RL1 3
RW1 4
RH1 ⁵
GND 6
166 RH3
15 RL2
14 RW2
13 RH2
12 SCL
11 SDA
7 8 9 10
ISL23348
V_CC
POWER UP
INTERFACE
CONTROL
AND
STATUS
LOGIC
GND
WR0
VOLATILE
REGISTER
WR1
VOLATILE
REGISTER
WR2
VOLATILE
REGISTER
WR3
VOLATILE
REGISTER
RH0
RW0
RL0
RH1
RW1
RL1
RH2
RW2
RL2
RH3
RW3
RL3
Pin Descriptions
TSSOP QFN SYMBOL
DESCRIPTION
1
19
RL0 DCP0 “low” terminal
2
20
RW0 DCP0 wiper terminal
3
1
V_CC Analog power supply.
Range 1.7V to 5.5V
4
2
RH0 DCP0 “high” terminal
5
3
RL1 DCP1 “low” terminal
6
4
RW1 DCP1 wiper terminal
7
5
RH1 DCP1 “high” terminal
8
6
GND Ground pin
9
7
V_LOGIC I²C bus /logic supply. Range 1.2V to 5.5V
10
8
A0 Logic Pin - Hardwire slave address pin for
I²C serial bus.
Range: V_LOGIC or GND
11
9
A1 Logic Pin - Hardwire slave address pin for
I²C serial bus.
Range: V_LOGIC or GND
12
10
A2 Logic Pin - Hardwire slave address pin for
I²C serial bus.
Range: V_LOGIC or GND
13
11
SDA Logic Pin - Serial bus data input/open
drain output
14
12
SCL Logic Pin - Serial bus clock input
15
13
RH2 DCP2 “high” terminal
16
14
RW2 DCP2 wiper terminal
17
15
RL2 DCP2 “low” terminal
18
16
RH3 DCP3 “high” terminal
19
17
RW3 DCP3 wiper terminal
20
18
RL3 DCP3 “low” terminal
2
FN7903.1
August 24, 2011