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ISL23348 Datasheet, PDF (16/19 Pages) Intersil Corporation – Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)
ISL23348
SCL FROM
MASTER
1
SDA OUTPUT FROM
TRANSMITTER
8
9
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH IMPEDANCE
START
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
SIGNALS FROM
THE MASTER
S
WRITE
T
A
R IDENTIFICATION
T
BYTE
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
1 0 1 0 A2A1A0 0 0 0 0
SIGNALS FROM
THE SLAVE
A
A
A
C
C
C
K
K
K
FIGURE 29. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 0
ADDRESS
BYTE
S
READ
T
A IDENTIFICATION
R BYTE WITH
T
R/W = 1
A
A
C
C
K
K
S
AT
CO
KP
SIGNAL AT SDA 1 0 1 0 A2A1 A0 0 0 0 0
A
SIGNALS FROM
C
THE SLAVE
K
1 0 1 0 A2 A1 A0 1
A
A
C
C FIRST READ
K
K DATA BYTE
FIGURE 30. READ SEQUENCE
LAST READ
DATA BYTE
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23348 responds
with an ACK. The data is transferred from I2C block to the
corresponding register at the 9th clock of the data byte and
device enters its standby state (see Figures 28 and 29).
It is possible to perform a sequential Write to all DCP channels
via a single Write operation. The command is initiated by sending
an additional Data Byte after the first Data byte instead of
sending a STOP condition.
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 30). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23348 responds
with an ACK; then the ISL23348 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 30).
16
FN7903.1
August 24, 2011