ISL23348 Datasheet, PDF (7/19 Pages) Intersil Corporation – Quad, 128 Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23348
Operating Specifications V_CC = 2.7V to 5.5V, V_LOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 20) (Note 8) (Note 20) UNITS
t_DCP Wiper Response Time
W option; SCL rising edge at the acknowledge bit
0.4
µs
after data byte to wiper new position from 10% to
90% of the final value.
U option; SCL rising edge of the acknowledge bit
1.5
µs
after data byte to wiper new position from 10% to
90% of the final value.
T option; SCL rising edge of the acknowledge bit
3.5
µs
after data byte to wiper new position from 10% to
90% of the final value.
tShdnRec DCP Recall Time from Shutdown Mode SCL rising edge of the acknowledge bit after ACR
1.5
µs
data byte to wiper recalled position and RH
connection
V_CC, V_LOGIC V_{CC ,}V_LOGIC Ramp Rate
Ramp
(Note 21)
Ramp monotonic at any level
0.01
50 V/ms
Serial Interface Specification For SCL, SDA, A0, A1, A2 unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 20) (Note 8) (Note 20) UNITS
V_IL
V_IH
Hysteresis
V_OL
C_pin
f_SCL
t_sp
Input LOW Voltage
Input HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW Voltage
SDA, SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
V_LOGIC > 2V
V_LOGIC < 2V
I_OL = 3mA, V_LOGIC > 2V
I_OL = 1.5mA, V_LOGIC < 2V
Any pulse narrower than the max spec is
suppressed
-0.3
0.7 x V_LOGIC
0.05 x V_LOGIC
0.1 x V_LOGIC
0
0.3 x V_LOGIC V
V_LOGIC + 0.3 V
V
V
0.4
V
0.2 x V_LOGIC V
10
pF
400
kHz
50
ns
t_AA
SCL Falling Edge to SDA Output SCL falling edge crossing 30% of V_LOGIC, until
Data Valid
SDA exits the 30% to 70% of V_LOGIC window
t_BUF
Time the Bus Must be Free Before SDA crossing 70% of V_LOGIC during a STOP
1300
the Start of a New Transmission condition, to SDA crossing 70% of V_LOGIC during
the following START condition
900
ns
ns
t_LOW
Clock LOW Time
Measured at the 30% of V_LOGIC crossing
1300
ns
t_HIGH
Clock HIGH Time
Measured at the 70% of V_LOGIC crossing
600
ns
t_SU:STA START Condition Set-up Time
SCL rising edge to SDA falling edge; both crossing
600
ns
70% of V_LOGIC
t_HD:STA START Condition Hold Time
From SDA falling edge crossing 30% of V_LOGIC to
600
ns
SCL falling edge crossing 70% of V_LOGIC
t_SU:DAT Input Data Set-up Time
From SDA exiting the 30% to 70% of V_LOGIC
100
ns
window, to SCL rising edge crossing 30% of
V_LOGIC
t_HD:DAT Input Data Hold Time
From SCL falling edge crossing 70% of V_LOGIC to
0
ns
SDA entering the 30% to 70% of V_LOGIC window
7
FN7903.1
August 24, 2011