CD4034BMS Datasheet, PDF (8/14 Pages) Intersil Corporation – CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register

CD4034BMS
“A” OR “B”
DATA
INPUTS
“B” OR “A”
DATA
OUTPUTS
tPLH
tTLH
tPHL
trCL
CLOCK
INPUT
tfCL
VDD
90%
50%
10% ₀
tTHL
90%
VDD
50%
10% ₀
INPUT
**
tSLH
OUTPUT
**
tSHL
tTLH
tTHL
50%
0
VDD
90%
50%
10% ₀
tPLH
tPHL
*Input refers to any of the “A” or “B” data inputs, “A” ENABLE,
SERIAL INPUT, A/B, P/S, or A/S inputs
**tSLH and tSHL are Set-Up times
FIGURE 1. ASYNCHRONOUS OPERATION PROPAGATION
DELAY TIME AND TRANSITION TIME
FIGURE 2. SYNCHRONOUS OPERATION PROPAGATION DE-
LAY TIMES, TRANSITION TIMES, AND SET-UP
TIMES
CLOCK
A ENABLE
P/S
A/B
A/S
SERIAL DATA
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
B DATA LINES ARE OUTPUTS
FIGURE 3. TIMING DIAGRAM
A DATA
LINES ARE
OUTPUTS
7-844