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CD4034BMS Datasheet, PDF (11/14 Pages) Intersil Corporation – CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register | |||
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CD4034BMS
VSS
PROTECTION NETWORK
ON ALL âAâ AND âBâ
DATA INPUTS
K
p
n
K
P/S
CLM
An
CLS
1 OF 8 STAGES
M
Qâ
Qâ
VDD
SERIAL
DATA
VDD
D
p
n
P/S
p
n
CLM
CLM
p
n
p
n
CLS
CLS
p
n
L CLM
CLS
VSS
PROTECTION NETWORK
ON SERIAL DATA INPUT
p
n
L
Bn
FIGURE 11. REGISTER STAGE LOGIC DIAGRAM (1 OF 8 STAGES)
M
VSS
N
VDD
Qâ
N
VSS
Q (TO NEXT STAGE D)
TRUTH TABLE REGISTER INPUT-LEVELS AND
RESULTING REGISTER OPERATION
âAâ
ENABLE P/S
A/B
A/S
OPERATION*
0
0
0
X
Serial Mode; Synch. Serial Data Input, âAâ Parallel Data Outputs Disabled
0
0
1
X
Serial Mode; Synch. Serial Data Input, âBâ Parallel Data Output
0
1
0
0
Parallel Mode; âBâ Synch. Parallel Data Inputs, âAâ Parallel Data Outputs Disabled
0
1
0
1
Parallel Mode; âBâ Asynch. Parallel Data Inputs, âAâ Parallel Data Outputs Disabled
0
1
1
0
Parallel Mode; âAâ Parallel Data Inputs Disabled, âBâ Parallel Data Outputs, Synch. Data
Recirculation
0
1
1
1
Parallel Mode; âAâ Parallel Data Inputs Disabled, âBâ Parallel Data Outputs, Asynch. Data
Recirculation
1
0
0
X
Serial Mode; Synch. Serial Data Input, âAâ Parallel Data Output
1
0
1
X
Serial Mode; Synch. Serial Data Input, âBâ Parallel Data Output
1
1
0
0
Parallel Mode; âBâ Synch. Parallel Data Input, âAâ Parallel Data Output
1
1
0
1
Parallel Mode; âBâ Asynch. Parallel Data Input, âAâ Parallel Data Output
1
1
1
0
Parallel Mode; âAâ Synch, Parallel Data Input, âBâ Parallel Data Output
1
1
1
1
Parallel Mode; âAâ Asynch. Parallel Data Input, âBâ Parallel Data Output
*Outputs change at positive transition of clock in the serial mode and when the A/S control input is âlowâ in the parallel mode. During
transfer from parallel to serial operation A/S should remain low in order to prevent DS transfer into Flip Flops.
1 = High Level
0 = Low Level
X = Donât Care
7-847
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