CD4034BMS Datasheet, PDF (13/14 Pages) Intersil Corporation – CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register

Applications (Continued)
SHIFT LEFT OUTPUT
“A” ENABLE
SHIFT LEFT/
SHIFT RIGHT
CD4034BMS
“A” PARALLEL DATA
SHIFT RIGHT
INPUT
AE 1
8
SI
REG. 1
P/S
CLOCK
CD4034
A/S
CL
A/S
PARALLEL
ENTRY
A/B 1
VDD
AE 1 A PARALLEL DATA 8
SI
P/S
REG. 3
A/S
CD4034
CL
A/B 1 ^{B PARALLEL DATA 8}
VDD
AE 1
SI
P/S
A/S
CL
A/B 1
AE
P/S
“A” PARALLEL DATA
SHIFT RIGHT
OUTPUT
8
REG. 2
CD4034
SHIFT
LEFT INPUT*
A/S
CL
AE
AE 1 A PARALLEL DATA 8
SI
P/S
REG. 4
A/S
CD4034
CL
A/B 1 ^{B PARALLEL DATA 8}
FIGURE 15. SHIFT RIGHT/SHIFT LEFT WITH PARALLEL INPUTS
A “High” (“Low”) on the shift Left/Shift Right input allows
serial data on the Shift Left Input (Shift Right Input) to enter
the register on the positive transition of the clock signal. A
“high” on the “A” Enable Input disables the “A” parallel data
lines Reg. 1 and 2 and enables the “A” data lines on regis-
ters 3 and 4 and allows parallel data into registers 1 and 2.
Other logic schemes may be used in place of registers 3 and
4 for parallel loading.
When parallel inputs are not used Reg. 3 and 4 and associ-
ated logic are not required.
* Shift left input must be disabled during parallel entry.
AE
SERIAL
DATA
SI
VDD
A/B
A/S
CLOCK
CL
P/S
A PARALLEL DATA
CD4034
B PARALLEL DATA
CD4016
N STAGE SELECTION
SAMPLE/HOLD
CD4016
N=1-8
SERIAL
OUTPUT
SERIAL DATA
VDD
A/S
CLOCK
P/S
AE 1
8
SI
“A” PARALLEL DATA
A/B
CD4034
A/S
CL
“B” PARALLEL DATA
P/S 1
8
TO DISPLAY ETC
FIGURE 16. N-STAGE SHIFT REGISTER WITH FIXED SERIAL
OUTPUT LINE
FIGURE 17. SAMPLE AND HOLD REGISTER - SERIAL/PARAL-
LEL IN - PARALLEL OUT
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