CD4034BMS Datasheet, PDF (12/14 Pages) Intersil Corporation – CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register

Applications
CD4034BMS
VDD
VDD
MEMORY
UNIT
SERIAL
DATA
VDD
P/S
A/S
CL
AE _{A PARALLEL}
SI
DATA
A/B _CD4034
A/S
CL ^{B PARALLEL}
P/S
DATA
VDD
SERIAL
DATA
AE _{A PARALLEL}
SI
DATA
A/B _CD4034
A/S
CL ^{B PARALLEL}
P/S
DATA
SERIAL
DATA
FIGURE 12. 16-BIT PARALLEL IN/PARALLEL OUT, PARALLEL IN/SERIAL OUT,
SERIAL IN/PARALLEL OUT SERIAL IN/SERIAL OUT REGISTER
“A” ENABLE
SERIAL
DATA
AE _{A PARALLEL}
SI
DATA
A/B _CD4034
A/S
CL ^{B PARALLEL}
P/S
DATA
SERIAL
DATA
AE _{A PARALLEL}
SI
DATA
A/B
A/S
CD4034
CL ^{B PARALLEL}
P/S
DATA
SERIAL
DATA
A/B
CL
FIGURE 13. 16-BIT SERIAL IN/GATED PARALLEL OUT REGISTER
BUS LINES
(SINGLE)
DOUBLE - BUS SYSTEM
(ENABLE INPUTS ON BOTH SIDES)
P/S
AE
1
1
2 CD4034
2
3
W REG
3
4
5B
4
A5
6
6
7
7
8
8
SI A/B A/S CL
AE
P/S
1
1
2 _X(1) 2
3 _REG 3
4A _B4
5 _CD4034 5
6
6
7
7
8
8
SI A/B A/S CL
P/S
AE
1
1
2 _X(2) 2
3 _REG 3
4B _A4
5
5
CD4034
6
6
7
7
8
8
SI A/B A/S CL
TO 2ND
BUS
SYSTEM
PERIPHERAL
UNIT
SI A/B A/S CL
P/S
AE
1
1
2
2
3
Y REG
3
4
5B
4
A5
6 ^CD4034
6
7
7
8
8
SI A/B A/S CL
AE
1
P/S
1
2
2
3
Z REG
3
4
5A
4
B5
6 ^CD4034
6
7
7
8
8
ARITHMETIC
UNIT
THE “A” ENABLE (AE) AND A/B SIGNALS CONTROL ALL
COMBINATIONS OF TRANSFER BETWEEN THE REGISTERS
AND BUS SYSTEMS
FIGURE 14. SINGLE AND DOUBLE-BUS SYSTEMS
7-848