CD4034BMS Datasheet, PDF (5/14 Pages) Intersil Corporation – CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register

Specifications CD4034BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V
Input Voltage Low
Input Voltage High
Propagation Delay
Parallel In to Parallel Out
Propagation Delay
Serial to Parallel Out
Propagation Delay 3-State
AE to Out ‘A’
Propagation Delay 3-State
AE to Out ‘A’
Transition Time
Maximum Clock Input
Frequency
Minimum Data Setup
Time
Serial Data to Clock
Minimum Data Setup
Time Parallel Data to
Clock
Minimum Clock Pulse
Width
Maximum Clock Rise and
Fall Time (Note 5)
Minimum High Level
Pulse Width AE, P/S, A/S
Input Capacitance
VIL
VIH
TPHL
TPLH
TPHL
TPLH
TPLZ
TPHZ
TPZL
TPZH
TTLH
TTHL
FCL
TS
TS
TW
TRCL
TFCL
TW
CIN
VDD = 10V, VOH > 9V,
VOL < 1V
VDD = 10V, VOH > 9V,
VOL < 1V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
NOTES
1, 2
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE MIN
+125^oC
-
-55^oC
-
+25^oC, +125^oC,
-
-55^oC
+25^oC, +125^oC, +7
-55^oC
+25^oC
-
+25^oC
-
+25^oC
700
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
5
+25^oC
7
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
+25^oC
-
MAX
-2.4
-4.2
3
UNITS
mA
mA
V
-
V
240
ns
170
ns
-
ns
240
ns
170
ns
160
ns
120
ns
160
ns
120
ns
100
ns
80
ns
-
MHz
-
MHz
160
ns
60
ns
40
ns
50
ns
30
ns
20
ns
250
ns
100
ns
70
ns
15
µs
15
µs
15
µs
350
ns
140
ns
80
ns
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, tRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
7-841