80C88_08 Datasheet, PDF (8/38 Pages) Intersil Corporation – CMOS 8-/16-Bit Microprocessor

80C88
.
7
0
FFFFFH
64K-BIT
CODE SEGMENT
XXXXOH
+ OFFSET
STACK SEGMENT
SEGMENT
REGISTER FILE
CS
SS
DS
ES
WORD
LSB
BYTE
MSB
DATA SEGMENT
EXTRA SEGMENT
00000H
FIGURE 1. MEMORY ORGANIZATION
All memory references are made relative to base addresses
contained in high speed segment registers. The segment
types were chosen based on the addressing needs of
programs. The segment register to be selected is
automatically chosen according to specific rules as shown in
Table1. All information in one segment type share the same
logical attributes (e.g., code or data). By structuring memory
into relocatable areas of similar characteristics and by
automatically selecting segment registers, programs are
shorter, faster, and more structured.
TABLE 1.
MEMORY
REFERENCE
NEED
SEGMENT
REGISTER
USED
SEGMENT
SELECTION RULE
Instructions
CODE (CS) Automatic with all instruction
prefetch.
Stack
STACK (SS)
All stack pushes and pops.
Memory references relative to
BP base register except data
references.
Local Data
DATA (DS)
Data references when: relative
to stack, destination of string
operation, or explicitly
overridden.
External Data
(Global)
EXTRA (ES) Destination of string
operations: Explicitly selected
using a segment override.
Word (16-bit) operands can be located on even or odd
address boundaries. For address and data operands, the
least significant byte of the word is stored in the lower valued
address location and the most significant byte in the next
higher address location.
The BIU will automatically execute two fetch or write cycles
for 16-bit operands.
Certain locations in memory are reserved for specific CPU
operations. (See Figure 2). Locations from addresses
FFFF0H through FFFFFH are reserved for operations
including a jump to initial system initialization routine.
Following RESET, the CPU will always begin execution at
location FFFF0H where the jump must be located. Locations
00000H through 003FFH are reserved for interrupt
operations. Each of the 256 possible interrupt service
routines is accessed through its own pair of 16-bit pointers -
segment address pointer and offset address pointer. The
first pointer, used as the offset address, is loaded into the IP,
and the second pointer, which designates the base address,
is loaded into the CS. At this point program control is
transferred to the interrupt routine. The pointer elements are
assumed to have been stored at their respective places in
reserved memory prior to the occurrence of interrupts.
Minimum and Maximum Modes
The requirements for supporting minimum and maximum
80C88 systems are sufficiently different that they cannot be
done efficiently with 40 uniquely defined pins. Consequently,
the 80C88 is equipped with a strap pin (MN/MX) which
defines the system configuration. The definition of a certain
subset of the pins changes, dependent on the condition of
the strap pin. When the MN/MX pin is strapped to GND, the
80C88 defines pins 24 through 31 and 34 in maximum
mode. When the MN/MX pins is strapped to V_CC, the 80C88
generates bus control signals itself on pins 24 through 31
and 34.
The minimum mode 80C88 can be used with either a
muliplexed or demultiplexed bus. This architecture provides
the 80C88 processing power in a highly integrated form.
The demultiplexed mode requires one latch (for 64k address
ability) or two latches (for a full megabyte of addressing). An
82C86 or 82C87 transceiver can also be used if data bus
buffering is required. (See Figure 3). The 80C88 provides
DEN and DT/R to control the transceiver, and ALE to latch
the addresses. This configuration of the minimum mode
provides the standard demultiplexed bus structure with
heavy bus buffering and relaxed bus timing requirements.
The maximum mode employs the 82C88 bus controller (See
Figure 4). The 82C88 decode status lines S0, S1 and S2,
and provides the system with all bus control signals. Moving
the bus control to the 82C88 provides better source and sink
current capability to the control lines, and frees the 80C88
pins for extended large system features. Hardware lock,
queue status, and two request/grant interfaces are provided
by the 80C88 in maximum mode. These features allow
coprocessors in local bus and remote bus configurations.
8
FN2949.4
February 22, 2008