80C88_08 Datasheet, PDF (12/38 Pages) Intersil Corporation – CMOS 8-/16-Bit Microprocessor

80C88
Designers familiar with the 8085 or upgrading an 8085
design should note that the 8085 addresses I/O with an 8-bit
address on both halves of the 16-bit address bus. The
80C88 uses a full 16-bit address on its lower 16 address
lines.
External Interface
Processor Reset and Initialization
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 80C88 RESET is
required to be HIGH for greater than four clock cycles. The
80C88 will terminate operations on the high-going edge of
RESET and will remain dormant as long as RESET is HIGH.
The low-going transition of RESET triggers an internal reset
sequence for approximately 7 clock cycles. After this interval
the 80C88 operates normally, beginning with the instruction
in absolute location FFFFOH (see Figure 2). The RESET
input is internally synchronized to the processor clock. At
initialization, the HIGH to LOW transition of RESET must
occur no sooner than 50μs after power up, to allow complete
initialization of the 80C88.
NMI will not be recognized if asserted prior to the second
CLK cycle following the end of RESET.
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate the need for pull-up/down
resistors, “bus-hold” circuitry has been used on 80C88 pins
2-16, 26-32 and 34-39 (see Figure 6A and 6B). These
circuits maintain a valid logic state if no driving source is
present (i.e., an unconnected pin or a driving source which
goes to a high impedance state).
To override the “bus hold” circuits, an external driver must be
capable of supplying 400μA minimum sink or source current
at valid input voltage levels. Since this “bus hold” circuitry is
active and not a “resistive” type element, the associated
power supply current is negligible. Power dissipation is
significantly reduced when compared to the use of passive
pull-up resistors.
Interrupt Operations
Interrupt operations fall into two classes: software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in the
instruction set description. Hardware interrupts can be
classified as nonmusical or maskable.
Interrupts result in a transfer of control to a new program
location. A 256 element table containing address pointers to
the interrupt service program locations resides in absolute
locations 0 through 3FFH (see Figure 2), which are reserved
for this purpose. Each element in the table is 4-bytes in size
and corresponds to an interrupt “type”. An interrupting
device supplies an 8-bit type number, during the interrupt
acknowledge sequence, which is used to vector through the
appropriate element to the new interrupt service program
location.
OUTPUT
DRIVER
BOND
PAD
EXTERNAL
PIN
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
FIGURE 6A. BUS HOLD CIRCUITRY PINS 2-16 AND 35-39
OUTPUT ^VCC
P
DRIVER
BOND
PAD
EXTERNAL
PIN
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
FIGURE 6B. BUS HOLD CIRCUITRY PINS 26-32 AND 34
FIGURE 6.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt
(NMI) pin which has higher priority than the maskable
interrupt request (INTR) pin. A typical use would be to
activate a power failure routine. The NMI is edge-triggered
on a LOW to High transition. The activation of this pin
causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than two clock cycles, but is not required to be
synchronized to the clock. An high going transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves (2-bytes in the case of
word moves) of a block type instruction. Worst case
response to NMI would be for multiply, divide, and variable
shift instructions. There is no specification on the occurrence
of the low-going edge; it may occur before, during, or after
the servicing of NMI. Another high-going edge triggers
another response if it occurs after the start of the NMI
procedure.
The signal must be free of logical spikes in general and be
free of bounces on the low-going edge to avoid triggering
extraneous responses.
Maskable Interrupt (INTR)
The 80C88 provides a singe interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable (IF) flag bit. The interrupt
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK.
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FN2949.4
February 22, 2008