80C88_08 Datasheet, PDF (11/38 Pages) Intersil Corporation – CMOS 8-/16-Bit Microprocessor

CLK
ALE
S2-S0
ADDR
STATUS
ADDR
ADDR DATA
RD, INTA
READY
DT/R
80C88
(4 + NWAIT) = TCY
(4 + NWAIT) = TCY
T1
T2
T3
TWAIT
T4
T1
T2
T3
TWAIT T4
GOES INACTIVE IN THE STATE
JUST PRIOR TO T4
A19-A16
S6-S3
A15-A8
A7-A0
BUS RESERVED ^D15-D0
FOR DATA IN
VALID
READY
WAIT
A19-A16
S6-S3
A15-A8
A7-A0
DATA OUT (D7-D0)
READY
WAIT
DEN
WP
S2
S1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
MEMORY ACCESS TIME
FIGURE 5. BASIC SYSTEM TIMING
TABLE 2.
S0
CHARACTERISTICS
0
Interrupt Acknowledge
1
Read I/O
0
Write I/O
1
Halt
0
Instruction Fetch
TABLE 3.
S4
S3
CHARACTERISTICS
0
0
Alternate Data (Extra Segment)
0
1
Stack
1
0
Code or None
1
1
Data
1
Read Data from Memory
0
Write Data to Memory
1
Passive (No Bus Cycle)
I/O Addressing
In the 80C88, I/O operations can address up to a maximum
of 64k I/O registers. The I/O address appears in the same
format as the memory address on bus lines A15-A0. The
address lines A19-A16 are zero in I/O operations. The
variable I/O instructions, which use register DX as a pointer,
have full address capability, while the direct I/O instructions
directly address one or two of the 256 I/O byte locations in
page 0 of the I/O address space. I/O ports are addressed in
the same manner as memory locations.
11
FN2949.4
February 22, 2008