ISL62773 Datasheet, PDF (7/37 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

Pin Configuration
ISL62773
ISL62773
(48 LD QFN)
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37
ISEN2_NB 1
NTC_NB 2
IMON_NB 3
SVC 4
VR_HOT_L 5
SVD 6
VDDIO 7
SVT 8
ENABLE 9
GND PAD
(BOTTOM)
36 BOOTX
35 VIN
34 BOOT2
33 UGATE2
32 PHASE2
31 LGATE2
30 VDDP
29 VDD
28 PWM_Y
PWROK 10
IMON 11
NTC 12
27 LGATE1
26 PHASE1
25 UGATE1
13 14 15 16 17 18 19 20 21 22 23 24
Pin Descriptions
PIN NUMBER
1
SYMBOL
ISEN2_NB
2
NTC_NB
3
IMON_NB
4
SVC
5
VR_HOT_L
6
SVD
7
VDDIO
8
SVT
9
ENABLE
10
PWROK
11
IMON
12
NTC
13
ISEN3
7
DESCRIPTION
Individual current sensing for Channel 2 of the Northbridge VR. When ISEN2_NB is pulled to +5V, the
controller will disable Channel 2 and the Northbridge VR will run single-phase.
Thermistor input to VR_HOT_L circuit to monitor Northbridge VR temperature.
Northbridge output current monitor. A current proportional to the Northbridge VR output current is
sourced from this pin.
Serial VID clock input from the CPU processor master device.
Thermal indicator signal to AMD CPU. Thermal overload open drain output indicator active LOW.
Serial VID data bi-directional signal from the CPU processor master device to the VR.
VDDIO is the processor memory interface power rail and this pin serves as the reference to the controller
IC for this processor I/O signal level.
Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly
complete signal provided on from this pin.
Enable input. A high level logic on this pin enables both VRs.
System power good input. When this pin is high, the SVI 2 interface is active and the I²C protocol is
running. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This
pin must be low prior to the ISL62773 PGOOD output going high per the AMD SVI 2.0 Controller
Guidelines.
Core output current monitor. A current proportional to the Core VR output current is sourced from this pin.
Thermistor input to VR_HOT_L circuit to monitor Core VR temperature.
ISEN3 is the individual current sensing for Channel 3. When ISEN3 is pulled to +5V, the controller disables
Channel 3, and the Core VR runs in two-phase mode.
March 7, 2012
FN8263.0