ISL62773 Datasheet, PDF(29/37 Page) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

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ISL62773 Datasheet, PDF (29/37 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

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ISL62773

ISUM+

FIGURE 23. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS

FIGURE 24. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL

FIGURE 25. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE

RING

BACK

FIGURE 26. OUTPUT VOLTAGE RING-BACK PROBLEM

Rntcs

Rntc

Cn.1

OPTIONAL

Cn.2 Vcn

ISUM-

Rip Cip

OPTIONAL

FIGURE 27. OPTIONAL CIRCUITS FOR RING-BACK REDUCTION

Figure 26 shows the output voltage ring-back problem during

load transient response. The load current io has a fast step

change, but the inductor current iL cannot accurately follow.

Instead, iL responds in first-order system fashion due to the

nature of the current loop. The ESR and ESL effect of the output

capacitors makes the output voltage Vo dip quickly upon load

current change. However, the controller regulates Vo according to

the droop current idroop, which is a real-time representation of iL;

therefore, it pulls Vo back to the level dictated by iL, causing the

ring-back problem. This phenomenon is not observed when the

output capacitor has very low ESR and ESL, as is the case with all

ceramic capacitors.

Figure 27 shows two optional circuits for reduction of the

ring-back. Cn is the capacitor used to match the inductor time

constant. It usually takes the parallel of two (or more) capacitors

to get the desired value. Figure 27 shows that two capacitors

(Cn.1 and Cn.2) are in parallel. Resistor Rn is an optional

component to reduce the Vo ring-back. At steady state, Cn.1 +

Cn.2 provides the desired Cn capacitance. At the beginning of io

change, the effective capacitance is less because Rn increases

the impedance of the Cn.1 branch. As Figure 24 shows, Vo tends

to dip when Cn is too small, and this effect reduces the Vo

ring-back. This effect is more pronounced when Cn.1 is much

larger than Cn.2. It is also more pronounced when Rn is bigger.

However, the presence of Rn increases the ripple of the Vn signal

if Cn.2 is too small. It is recommended to keep Cn.2 greater than

2200pF. The Rn value usually is a few ohms. Cn.1, Cn.2 and Rn

values should be determined through tuning the load transient

response waveforms on an actual board.

Rip and Cip form an R-C branch in parallel with Ri, providing a

lower impedance path than Ri at the beginning of io change. Rip

and Cip do not have any effect at steady state. Through proper

selection of Rip and Cip values, idroop can resemble io rather than

iL, and Vo will not ring back. The recommended value for Rip is

100ï. Cip should be determined through tuning the load

transient response waveforms on an actual board. The

recommended range for Cip is 100pF~2000pF. However, it

should be noted that the Rip -Cip branch may distort the idroop

waveform. Instead of being triangular as the real inductor

current, idroop may have sharp spikes, which may adversely

affect idroop average value detection and therefore may affect

OCP accuracy. User discretion is advised.

March 7, 2012

FN8263.0

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