ISL62773 Datasheet, PDF (27/37 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL62773
Thermal Monitor [NTC, NTC_NB]
The ISL62773 features two thermal monitors which use an
external resistor network which includes an NTC thermistor to
monitor motherboard temperature and alert the AMD CPU of a
thermal issue. Figure 20 shows the basic thermal monitor circuit
on the Core VR NTC pin. The Northbridge VR features the same
thermal monitor. The controller drives a 30µA current out of the
NTC pin and monitors the voltage at the pin. The current flowing
out of the NTC pin creates a voltage that is compared to a
warning threshold of 640mV. When the voltage at the NTC pin
falls to this warning threshold or below, the controller asserts
VR_HOT_L to alert the AMD CPU to throttle back load current to
stabilize the motherboard temperature. A thermal fault counter
begins counting toward a minimum shutdown time of 100µs.
The thermal fault counter is an up/down counter, so if the
voltage at the NTC pin rises above the warning threshold, it will
count down and extend the time for a thermal fault to occur. The
warning threshold does have 20mV of hysteresis.
If the voltage at the NTC pin continues to fall down to the
shutdown threshold of 580mV or below, the controller goes into
shutdown and triggers a thermal fault. The PGOOD pin is pulled
low and tri-states the power MOSFETs. A fault on either side will
shutdown both VRs.
NTC
R_p
+
V_{NTC RNTC}
-
R_s
INTERNAL TO
ISL62773
30µA
VR_HOT_L
+V
R
MONITOR
Warning Shutdown
640mV 580mV
FIGURE 20. CIRCUITRY ASSOCIATED WITH THE THERMAL MONITOR
FEATURE OF THE ISL62773
As the board temperature rises, the NTC thermistor resistance
decreases and the voltage at the NTC pin drops. When the
voltage on the NTC pin drops below the over-temperature trip
threshold, then VR_HOT is pulled low. The VR_HOT signal is used
to change the CPU operation and decrease power consumption.
With the reduction in power consumption by the CPU, the board
temperature decreases and the NTC thermistor voltage rises.
Once the over-temperature threshold is tripped and VR_HOT is
taken low, the over-temperature threshold changes to the reset
level. The addition of hysteresis to the over-temperature
threshold prevents nuisance trips. Once both pin voltages exceed
the over-temperature reset threshold, the pull-down on VR_HOT
is released. The signal changes state and the CPU resumes
normal operation. The over-temperature threshold returns to the
trip level.
Table 13 summarizes the fault protections.
TABLE 13. FAULT PROTECTION SUMMARY
FAULT TYPE
FAULT DURATION
BEFORE
PROTECTION
PROTECTION
ACTION
FAULT
RESET
Overcurrent
Phase Current
Unbalance
Way-Overcurrent
(1.5xOC)
7.5µs to 11.5µs
1ms
PWM tri-state,
PGOOD latched
low
Undervoltage
-325mV
Overvoltage
+325mV
Immediately
PGOOD latched
low.
PWM tri-state. ^ENABLE
toggle or
PGOOD latched _{VDD toggle}
low.
Actively pulls the
output voltage to
below VID value,
then tri-state.
NTC Thermal
100µs min
PGOOD latched
low.
PWM tri-state.
Fault Recovery
All of the previously described fault conditions can be reset by
bringing ENABLE low or by bringing VDD below the POR
threshold. When ENABLE and VDD return to their high operating
levels, the controller resets the faults and soft-start occurs.
Interface Pin Protection
The SVC and SVD pins feature protection diodes which must be
considered when removing power to VDD and VDDIO, but leaving
it applied to these pins. Figure 21 shows the basic protection on
the pins. If SVC and/or SVD are powered but VDD is not, leakage
current will flow from these pins to VDD.
SVC, SVD
INTERNAL TO
ISL62773
VDD
GND
FIGURE 21. PROTECTION DEVICES ON THE SVC AND SVD PINS
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March 7, 2012
FN8263.0