ISL62773 Datasheet, PDF (17/37 Pages) Intersil Corporation – Multiphase PWM Regulator for AMD Fusion™ Desktop CPUs Using SVI 2.0

ISL62773
Rdroop
+Vdroop-
FB
COMP
+
E/A
-
Idroop
 DAC
VDAC
+
INTERNAL TO IC
+
X1
-
VCCSENSE
VR LOCAL VO
“CATCH” RESISTOR
SVC
SVD
SVID[7:0]
RTN
VSSSENSE
VSS
“CATCH” RESISTOR
FIGURE 14. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
As the load current increases from zero, the output voltage
droops from the VID programmed value by an amount
proportional to the load current, to achieve the load line. The
ISL62773 can sense the inductor current through the intrinsic DC
Resistance (DCR) of the inductors (see Figures 3 and 4) or
through resistors in series with the inductors (see Figure 5). In
both methods, capacitor C_n voltage represents the total inductor
current. A droop amplifier converts C_n voltage into an internal
current source with the gain set by resistor R_i. The current source
is used for load line implementation, current monitoring and
overcurrent protection.
Figure 14 shows the load-line implementation. The ISL62773
drives a current source (I_droop) out of the FB pin, as described by
Equation 1.
I_droop
=
V_-----C----n-
R_i
(EQ. 1)
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding, thus sustaining the load-line accuracy with
reduced cost.
I_droop flows through resistor R_droop and creates a voltage drop as
shown in Equation 2.
V_droop
=
R_dr
oo
p



I_d
ro
o
p

54_{--}
(EQ. 2)
V
CC_S
E
N
S
E
+
V
dr
oop
=
V_DAC + VSS_SENSE
Rewriting Equation 3 and substituting Equation 2 gives
Equation 4 is the exact equation required for load-line
implementation.
(EQ. 3)
VCC_SENSE – VSS_SENSE = V_DAC – R_droop  I_droop  5  4
(EQ. 4)
The VCC_SENSE and VSS_SENSE signals come from the processor die.
The feedback is open circuit in the absence of the processor. As
Figure 14 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and to add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10~100, provide voltage
feedback if the system is powered up without a processor installed.
Phase Current Balancing
ISEN3
INTERNAL
TO IC
ISEN2
PHASE3
Risen
Cisen
PHASE2
Risen
Cisen
ISEN1
PHASE1
Risen
Cisen
L3
Rdcr3 _Rpcb3
IL3
L2
Rdcr2 _Rpcb2
VO
IL2
L1
Rdcr1 _Rpcb1
IL1
FIGURE 15. CURRENT BALANCING CIRCUIT
The ISL62773 monitors individual phase average current by
monitoring the ISEN1, ISEN2, and ISEN3 voltages. Figure 15
shows the recommended current balancing circuit for DCR
sensing. Each phase node voltage is averaged by a low-pass filter
consisting of R_isen and C_isen, and is presented to the
corresponding ISEN pin. R_isen should be routed to the inductor
phase-node pad in order to eliminate the effect of phase node
parasitic PCB DCR. Equations 5 through 7 give the ISEN pin
voltages:
V_ISEN1 = R_dcr1 + R_pcb1  I_L1
(EQ. 5)
V_droop is the droop voltage required to implement load line.
Changing R_droop or scaling I_droop can change the load line slope.
Since I_droop also sets the overcurrent protection level, it is
recommended to first scale I_droop based on OCP requirement.
Next, select an appropriate R_droop value to obtain the desired
load line slope.
Differential Sensing
Figure 14 also shows the differential voltage sensing scheme.
VCC_SENSE and VSS_SENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSS_SENSE voltage and adds it to the DAC output. The error
amplifier regulates the inverting and non-inverting input voltages
to be equal as shown in Equation 3:
V_ISEN2 = R_dcr2 + R_pcb2  I_L2
(EQ. 6)
V_ISEN3 = R_dcr3 + R_pcb3  I_L3
(EQ. 7)
where R_dcr1, R_dcr2 and R_dcr3 are inductor DCR; R_pcb1, R_pcb2
and R_pcb3 are parasitic PCB DCR between the inductor output
side pad and the output voltage rail; and I_L1, I_L2 and I_L3 are
inductor average currents.
The ISL62773 will adjusts the phase pulse-width relative to the
other phases to make V_ISEN1 = V_ISEN2 = V_ISEN3, thus to achieve
I_L1 = I_L2 = I_L3, when R_dcr1 = R_dcr2 = R_dcr3 and
R_pcb1 = R_pcb2 = R_pcb3.
17
March 7, 2012
FN8263.0