ISL28022_15 Datasheet, PDF (7/32 Pages) Intersil Corporation – Precision Digital Power Monitor

ISL28022
Electrical Specifications T_A = +25°C, V_CC = 3.3, VINP = V_BUS = 12V, V_SENSE = VINP-VINM = 32mV, unless otherwise specified. All
voltages with respect to GND pin. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
MAX
(Note 8)
TYP
(Note 8) UNIT
DC ACCURACY
ADC TIMING SPECS
ADC Resolution (Native)
Current Measurement Error
Current Measurement Error
Over-temperature
Bus Voltage Measurement Error
Bus Voltage Measurement Error
Over-temperature
PGA gain = /1, V_SENSE = ±320mV
T_A = +25°C
T_A = -40°C to +85°C
T_A = -40°C to +125°C
T_A = +25°C
T_A = -40°C to +85°C
T_A = -40°C to +125°C
16
±0.2
±0.2
Bits
±0.3
%
±0.5
%
±1
%
±0.3
%
±0.5
%
±1
%
t_s
ADC Conversion Time
Mode = 5 or 6
ADC setting = 0000
ADC setting = 0001
72
79.2
µs
132
145.2
µs
ADC setting = 0010
258
283.8
µs
ADC setting = 0011
508
558.8
µs
ADC setting = 1001
1.01
1.11
ms
ADC setting = 1010
2.01
2.21
ms
ADC setting = 1011
4.01
4.41
ms
ADC setting = 1100
8.01
8.81
ms
ADC setting = 1101
16.01
17.61
ms
ADC setting = 1110
32.01
35.21
ms
I²C INTERFACE SPECIFICATIONS
ADC setting = 1111
64.01
70.41
ms
V_IL
V_IH
Hysteresis
V_OL
SDA and SCL Input Buffer LOW Voltage
SDA and SCL Input Buffer HIGH Voltage
SDA and SCL Input Buffer Hysteresis
SDA Output Buffer LOW Voltage, Sinking V_CC = 5V, I_OL = 3mA
3mA
-0.3
0.3 x V_CC V
0.7 x V_CC
V_CC + 0.3 V
0.05 x V_CC
V
0
0.02
0.4
V
C_PIN
f_SCL
t_IN
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at SDA
and SCL Inputs
T_A = +25°C, f = 1MHz,
V_CC = 5V, V_IN = 0V,
V_OUT = 0V
Any pulse narrower than the max
spec is suppressed.
10
pF
400
kHz
50
ns
t_AA
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V_CC,
Valid
until SDA exits the 30% to 70% of V_CC
window.
900
ns
t_BUF
Time the Bus Must be Free Before the SDA crossing 70% of V_CC during a
1300
ns
Start of a New Transmission
STOP condition, to SDA crossing 70%
of V_CC during the following START
condition.
t_LOW
Clock LOW Time
Measured at the 30% of V_CC crossing. 1300
ns
t_HIGH
Clock HIGH Time
Measured at the 70% of V_CC crossing. 600
ns
t_SU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge.
600
ns
Both crossing 70% of V_CC.
t_HD:STA
START Condition Hold Time
From SDA falling edge crossing 30% 600
ns
of V_CC to SCL falling edge crossing
70% of V_CC.
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7
FN8386.7
October 2, 2015