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ISL28022_15 Datasheet, PDF (15/32 Pages) Intersil Corporation – Precision Digital Power Monitor
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ISL28022
BADC: Bus ADC Resolution/Averaging
Bits [10:7] of the configuration register sets the ADC resolution/
averaging when the ADC is configured in the VBUS mode. The
ADC can be configured versus bit accuracy. The bit accuracy
selections range from 12 to 15 bits. The ADC is configurable
versus the number of averages. The selection ranges from 2 to
128 samples. Table 6 shows the breakdown of each BADC
setting. The shaded row is the default setting upon power-up.
SADC: Shunt ADC Resolution/Averaging
Bits [10:7] of the configuration register sets the ADC resolution/
averaging when the ADC is configured in the VSHUNT mode. The
ADC can be configured versus bit accuracy. The bit accuracy
selections range from 12 to 15 bits. The ADC is configurable
versus number of averages. The selection ranges from 2 to 128
samples. Table 6 shows the break down of each SADC setting.
The shaded row is the default setting upon power-up.
MODE: Operating Mode
Bits [2:0] of the configuration register controls the state machine
within the chip. The state machine globally controls the overall
functionality of the chip. Table 7 shows the various states the
chip can be configured to, as well as the mode bit definitions to
achieve a desired state. The shaded row is the default setting upon
power-up.
ADC3
0
0
0
0
1
1
1
1
1
1
1
1
TABLE 6. ADC SETTINGS, APPLIES TO BOTH SADC AND BADC CONTROL
ADC2
ADC1
ADC0
MODE/SAMPLES
X
0
0
12-bit
X
0
1
13-bit
X
1
0
14-bit
X
1
1
15-bit
0
0
0
15-bit
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
CONVERSION TIME
72µs
132µs
258µs
508µs
508µs
1.01ms
2.01ms
4.01ms
8.01ms
16.01ms
32.01ms
64.01ms
MODE2
0
0
0
0
1
1
1
1
MODE1
0
0
1
1
0
0
1
1
TABLE 7. OPERATING MODE SETTINGS
MODE0
0
Power-down
1
Shunt voltage, triggered
0
Bus voltage, triggered
1
Shunt and bus, triggered
0
ADC off (disabled)
1
Shunt Voltage, continuous
0
Bus voltage, continuous
1
Shunt and bus, continuous
MODE
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FN8386.7
October 2, 2015
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