ISL28022_15 Datasheet, PDF (24/32 Pages) Intersil Corporation – Precision Digital Power Monitor

ISL28022
External Clock
+
ECLK
-
VTH
FUNCTION
GENERATOR
VBUS
VINP
VINM
ISL28022 DPM
VCC
ADC
16-BIT
REG
MAP
GND
SCL
SDA
A0
A1
3.3V
FIGURE 36. SIMPLIFIED SCHEMATIC OF THE ISL28022
SYNCHRONIZED TO A PWM SOURCE
An externally controlled clock allows measurements to be
synchronized to an event that is time dependent. The event could
be application generated, such as timing a current measurement
to a charging capacitor in a switch regulator application or the
event could be environmental. A voltage or current measurement
may be susceptible to crosstalk from a controlled source. Instead
of filtering the environmental noise from the measurement,
another approach would be to synchronize the measurement to
the source. The variability and accuracy of the measurement will
improve.
The ISL28022 has the functionality to allow for synchronization
to an external clock. The speed of the external clock combined
with the choice of the internal chip frequency division value
determines the acquisition times of the ADC. The internal system
clock frequency is 500kHz. The internal system clock is also the
ADC sampling clock. The acquisition times scale linearly from
500kHz. For example, an external clock frequency of 1MHz with
a frequency divide setting of 2 results in acquisition times that
equals the internal oscillator frequency when enabled. The
internal clock frequency of the ISL28022 should not exceed
500kHz. The ADC modulator is optimized for frequencies of
500kHz and below. Operating internal clock frequencies above
500kHz result in measurement accuracy errors due to the
modulator not having enough time to settle.
Suppose an external clock frequency of 1.0MHz is applied with a
divide by 8 internal frequency setting, the system clock speed is
125kHz or 4x slower than internal system clock. The acquisition
times for this example will increase by 4. For a S(B)ADC setting
of 3, the ISL28022 will have an acquisition time of 2.032ms
instead of 508µs.
ECLK/INT
Fclk_Sys
÷
+1
2X
FIGURE 37. SIMPLIFIED INTERNAL BLOCK CONNECTION OF THE
ECLK/INT PIN
The ECLK/INT pin connects to a buffer that drives a D-flip flop.
Figure 37 illustrates a simple schematic of the ECLK/INT pin
internal connection. The series of divide by 2 configured D-flip
flops are controlled by the CLKDIV bits from the Aux Control
Register. The buffer is a Schmitt triggered buffer. The bandwidth
of the buffer is 4MHz. Figure 38 shows the bandwidth of the
ECLK/INT pin.
5
CLKDIV = 5 (÷ 12)
4
SADC = 3
3
2
1
0
-1
1
10
EXTERNAL CLOCK FREQUENCY (MHz)
FIGURE 38. EXTERNAL CLOCK BANDWIDTH vs MEASUREMENT
ACCURACY
The V_SHUNT measurement error degrades at ECLK frequencies
above 4MHz. It is recommended that the ECLK does not exceed
4MHz. At ECLK frequencies below 2.5MHz or internal clock
frequencies of 208kHz, the clock frequency to modulator is too
slow allowing the charged capacitors to discharge due to
parasitic leakages. The capacitor discharge results in a
measurement error.
Over-ranging
It is not recommended to operate the ISL28022 outside the set
voltage range. In the event of measuring a shunt voltage beyond
the maximum set range (320mV) and lower than the clamp
voltage of the protection diode (1V), the measured output
reading may be within the accepted range but will be incorrect.
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FN8386.7
October 2, 2015