ISL28022_15 Datasheet, PDF (19/32 Pages) Intersil Corporation – Precision Digital Power Monitor

ISL28022
BUS VOLTAGE THRESHOLD REGISTER 07H
(READ/WRITE)
The V_BUS minimum and maximum threshold limits are set using
one register. The V_BUS value readings range from 0V to 60V.
Table 19 on page 18 shows the register configuration and bit
weights for the V_BUS threshold register. BMX bits represent the
upper limit threshold. BMN represents the lower threshold limit.
Equation 9 is the calculation used to convert the V_BUS threshold
binary value to decimal. Bit is the value of each bit set in the
V_BUS threshold register. The value is either 1 or a 0. The weight of
each bit is represented in Table 19. n is the bit number. The V_BUS
voltage threshold LSB is 256mV.
Vb _thresh
 ^{   7}

Bit_n Bit_Weight _n

 _{ VbThresh}

LSB
^{n  0}

(EQ. 9)
INTERRUPT STATUS REGISTER 08H (READ/WRITE)
The interrupt status register consists of a series of bit flags that
indicate if an ADC reading has exceeded the readings respective
limit. A 1 or high reading from a warning bit indicates the reading
has exceeded the limit. To clear a warning, write a 1 or high to
the set warning bit. Table 20 on page 18 shows the definition of
the interrupt status register.
BMNW is the bus voltage minimum warning. A 1 reading for this
bit indicates the bus reading is below the bus voltage minimum
threshold limit.
BMXW is the bus voltage maximum warning. A 1 reading for this
bit indicates the bus reading is above the bus voltage maximum
threshold limit.
SMNW is the shunt voltage minimum warning. A 1 reading for
this bit indicates the shunt reading is below the shunt voltage
minimum threshold limit.
SMXW is the shunt voltage maximum warning. A 1 reading for
this bit indicates the shunt reading is above the shunt voltage
maximum threshold limit.
AUX CONTROL REGISTER 09H (READ/WRITE)
The Aux control register controls the functionality of the
EXTCLK/INT pin of the ISL28022. Table 21 shows the definition
of the register.
FORCEINTR is the force interrupt bit. Programming a 1 to the bit
will force a 0 or a low at the EXTCLK/INT pin.
INTREN is the interrupt enable bit. Programming a 1 to the bit
will allow for a threshold measurement violation to set the state
of the EXTCLK/INT pin. With the INTREN set, any flag set from the
interrupt status register will change the state of the EXTCLK/INT
pin from 1 to a 0.
EXCLKEN is the external clock enable bit. Setting the bit enables
the external clock. This also changes the EXTCLK/INT pin from an
output to an input. The internal oscillator will shut down when the
bit is enabled.
EXTCLKDIV are the external clock divider bits. The bits control an
internal clock divider that are useful for fast system clocks. The
internal clock frequency from pin to chip is represented in
Equation 10:
freq _internal
f _EXTCLK
(EXTCLKDIV 1)2
(EQ. 10)
f_EXTCLK is the frequency of the signal driven to the EXTCLK/INT
pin. EXTCLKDIV is the decimal value of the clock divide bits.
Serial Interface
The ISL28022 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL28022 operates as a slave device in all
applications.
The ISL28022 uses two bytes to transfer all reads and writes. All
communication over the I²C interface is conducted by sending
the MSByte of each byte of data first, followed by the LSByte.
Protocol Conventions
For normal operation, data states on the SDA line can change
only during SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating START and STOP conditions
(see Figure 27). On power-up of the ISL28022, the SDA pin is in
the input mode.
All I²C interface operations must begin with a START condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
ISL28022 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 27). A START condition is ignored
during the power-up sequence.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW-to-HIGH transition of SDA while SCL is
HIGH (see Figure 27). A STOP condition at the end of a read
operation or at the end of a write operation places the device in its
standby mode.
SMBus Support
The ISL28022 supports SMBus protocol, which is a subset of the
global I²C protocol. SMBCLK and SMBDAT have the same pin
functionality as the SCL and SDA pins, respectively. The SMBus
operates at 100kHz.
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FN8386.7
October 2, 2015