ISL23418 Datasheet, PDF (7/20 Pages) Intersil Corporation – Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23418
Serial Interface Specification For SCK, SDI, SDO, CS, unless otherwise noted.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
(Note 20) (Note 8) (Note 20) UNITS
V_IL
Input LOW Voltage
-0.3
0.3 x V_LOGIC V
V_IH
Input HIGH Voltage
0.7 x V_LOGIC
V_LOGIC+ 0.3 V
Hysteresis SDI and SCK Input Buffer Hysteresis V_LOGIC > 2V
0.05 x V_LOGIC
V
V_LOGIC < 2V
0.1 x V_LOGIC
V_OL
SDO Output Buffer LOW Voltage
I_OL = 3mA, V_LOGIC > 2V
0
0.4
V
I_OL = 1.5mA, V_LOGIC < 2V
0.2 x V_LOGIC V
R_pu
SDO Pull-up Resistor Off-chip
Maximum is determined by t_RO and t_FO with
maximum bus load Cb = 30pF, f_SCK = 5MHz
1.5
kΩ
C_pin
SCK, SDO, SDI, CS Pin Capacitance
10
pF
f_SCK
SCK Frequency
V_LOGIC = 1.7V to 5.5V
5
MHz
V_LOGIC = 1.2V to 1.6V
1
MHz
t_CYC
SPI Clock Cycle Time
V_LOGIC ≥ 1.7V
200
ns
t_WH
SPI Clock High Time
V_LOGIC ≥ 1.7V
100
ns
t_WL
SPI Clock Low Time
V_LOGIC ≥ 1.7V
100
ns
t_LEAD
Lead Time
V_LOGIC ≥ 1.7V
250
ns
t_LAG
Lag Time
V_LOGIC ≥ 1.7V
250
ns
t_SU
SDI, SCK and CS Input Setup Time V_LOGIC ≥ 1.7V
50
ns
t_H
SDI, SCK and CS Input Hold Time
V_LOGIC ≥ 1.7V
50
ns
t_RI
SDI, SCK and CS Input Rise Time
V_LOGIC ≥ 1.7V
10
ns
t_FI
SDI, SCK and CS Input Fall Time
V_LOGIC ≥ 1.7V
10
20
ns
t_DIS
SDO Output Disable Time
V_LOGIC ≥ 1.7V
0
100
ns
t_SO
SDO Output Setup Time
V_LOGIC ≥ 1.7V
50
ns
t_V
SDO Output Valid Time
V_LOGIC ≥ 1.7V
150
ns
t_HO
SDO Output Hold Time
V_LOGIC ≥ 1.7V
0
ns
t_RO
SDO Output Rise Time
R_pu = 1.5k, Cbus = 30pF
60
ns
t_FO
SDO Output Fall Time
R_pu = 1.5k, Cbus = 30pF
60
ns
t_CS
CS Deselect Time
2
µs
NOTES:
8. Typical values are for T_A = +25°C and 3.3V supply voltages.
9. LSB = [V(RW)₁₂₇ – V(RW)₀]/127. V(RW)₁₂₇ and V(RW)₀ are V(RW) for the DCP register set to 7F hex and 00 hex, respectively. LSB is the incremental
voltage when changing from one tap to an adjacent tap.
10. ZS error = V(RW)₀/LSB.
11. FS error = [V(RW)₁₂₇ – V_CC]/LSB.
12. DNL = [V(RW)_i – V(RW)_i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
13. INL = [V(RW)_i – i • LSB – V(RW)₀]/LSB for i = 1 to 127
14.
TC_V
=
M_------a_---x_----(_--V_----(_--R_----W_------)_--i--)_{----–----}M_-----i_--n_----(_---V_---(_---R_----W_------)_--i--)
V ( R W i ( + 25 °C ) )
×
------¹----⁰----⁶-------
+ 165 °C
for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
and Min( ) is the minimum value of the wiper voltage over the temperature range.
15. MI = |RW₁₂₇ – RW₀|/127. MI is a minimum increment. RW₁₂₇ and RW₀ are the measured resistances for the DCP register set to 7F hex and 00
hex, respectively.
16. Roffset = RW₀/MI, when measuring between RW and RL.
Roffset = RW₁₂₇/MI, when measuring between RW and RH.
17. RDNL = (RW_i – RW_i-1)/MI -1, for i = 16 to 127.
18. RINL = [RW_i – (MI • i) – RW₀]/MI, for i = 16 to 127.
19.
TC_R =
-^[--^M-----^a----^x---⁽--^R-----ⁱ--⁾---–-----^M-----ⁱ--ⁿ----⁽--^R----ⁱ--⁾---^]
R i ( + 25 °C )
×
------¹----⁰----⁶-------
+ 165 °C
for i = 16 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7
FN7901.0
August 3, 2011