ISL23418 Datasheet, PDF (16/20 Pages) Intersil Corporation – Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23418
Applications Information
Communicating with ISL23418
Communication with ISL23418 is accomplished by using the SPI
interface through the ACR (address 10000b) and WR (address
00000b) registers.
The wiper of the potentiometer is controlled by the WR register.
Writes and reads can be made directly to these registers to
control and monitor the wiper position.
Daisy Chain Configuration
When an application needs more than one ISL23418, it can
communicate with all of them without additional CS lines by
daisy chaining the DCPs, as shown in Figure 29. In daisy chain
configuration, the SDO pin of the previous chip is connected to
the SDI pin of the following chip, and each CS and SCK pin is
connected to the corresponding microcontroller pin in parallel,
like regular SPI interface implementation. The daisy chain
configuration can also be used for simultaneous setting of
multiple DCPs. Note that the number of daisy chained DCPs is
limited only by the driving capabilities of the SCK and CS pins of
the microcontroller. For a larger number of SPI devices, buffering
of the SCK and CS lines is required.
Daisy Chain Write Operation
The write operation starts with a HIGH to LOW transition on the
CS line, followed by N number of two-byte write instructions on
the SDI line, with reversed chain access sequence. The
instruction byte + data byte for the last DCP in the chain go first,
as shown in Figure 30, where N is the number of DCPs in the
chain. Serial data is going through the DCPs from DCP0 to
DCP(N-1) as follows: DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1).
The write instruction is executed on the rising edge of CS for all N
DCPs simultaneously.
Daisy Chain Read Operation
The read operation consists of two parts. First, the read
instructions (N two-byte operations) are sent with a valid address.
Second, the requested data is read while sending NOP
instructions (N two-byte operations), as shown in
Figures 31 and 32.
First there is a HIGH-to-LOW transition on the CS line, followed by
N two-byte read instructions on the SDI line, with reversed chain
access sequence. The instruction byte + dummy data byte for the
last DCP in the chain goes first, followed by a LOW-to-HIGH
transition on the CS line. The read instructions are executed
during the second part of the read sequence. It also starts by a
HIGH-to-LOW transition on the CS line, followed by N number of
two-byte NOP instructions on the SDI line and a LOW-to-HIGH
transition of CS. The data is read on every even byte during the
second part of the read sequence, while every odd byte contains
code 111b followed by the address from which the data is being
read.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can exhibit noticeable voltage
transients or overshoot/undershoot, which results from the
sudden transition from a very low impedance “make” to a much
higher impedance “break” within a short period of time (<1µs).
Several code transitions, such as 0Fh to 10h, 1Fh to 20h,..., and
EFh to 7Fh, have higher transient glitch. Note that all switching
transients settle well within the settling time as stated in the
datasheet. A small capacitor can be added externally to reduce
the amplitude of these voltage transients, but this also reduces
the useful bandwidth of the circuit, which may not be a good
solution for some applications. Using fast amplifiers in a signal
chain for fast recovery may be a good idea in these cases.
V_LOGIC Requirements
Keeping V_LOGIC powered all the time during normal operation is
recommended. In cases in which turning V_LOGIC OFF is
necessary, grounding the V_LOGIC pin is recommended. Grounding
the V_LOGIC pin or both V_LOGIC and V_CC does not affect other
devices on the same bus. It is good practice to put a 1µF capacitor
in parallel with a 0.1µF decoupling capacitor close to the V_LOGIC pin.
V_CC Requirements and Placement
Putting a 1µF capacitor in parallel with a 0.1µF decoupling capacitor
close to the V_CC pin is recommended.
CS
SCK
MOSI
MISO
µC
DCP0
CS
SCK
SDI
SDO
N DCP IN A CHAIN
DCP1
CS
SCK
SDI
SDO
DCP2
CS
SCK
SDI
SDO
DCP(N-1)
CS
SCK
SDI
SDO
FIGURE 29. DAISY CHAIN CONFIGURATION
16
FN7901.0
August 3, 2011