ISL23418 Datasheet, PDF (13/20 Pages) Intersil Corporation – Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23418
Functional Pin Descriptions
Potentiometers Pins
RH AND RL
The high (RH) and low (RL) terminals of the ISL23418 are
equivalent to the fixed terminals of a mechanical potentiometer.
The RH and RL are referenced to the relative position of the wiper
and not to the voltage potential on the terminals. With the WR
register set to 127 decimal, the wiper is closest to RH, and with
the WR register set to 0, the wiper is closest to RL.
RW
RW is the wiper terminal, and it is equivalent to the moveable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WR register.
Bus Interface Pins
SERIAL CLOCK (SCK)
The SCK input is the serial clock of the SPI serial interface.
SERIAL DATA INPUT (SDI)
SDI is a serial data input pin for the SPI interface. SDI receives
operation code, wiper address and data from the SPI remote
host device. The data bits are shifted in at the rising edge of the
serial clock, SCK, while CS input is low.
SERIAL DATA OUTPUT (SDO)
SDO is a serial data output pin. During a read cycle, the data bits
are shifted out on the falling edge of the serial clock SCK and are
available to the master on the following rising edge of SCK.
The output type is configured through ACR[1] bit for Push-Pull or
Open Drain operation. Default setting for this pin is Push-Pull. An
external pull-up resistor is required for Open Drain output
operation. When CS is HIGH, the SDO pin is in tri-state (Z) or
high-tri-state (Hi-Z), depending on the selected configuration.
CHIP SELECT (CS)
CS LOW enables the ISL23418, placing it in the active power
mode. A HIGH to LOW transition on CS is required prior to the
start of any operation after power-up. When CS is HIGH, the
ISL23418 is deselected, the SDO pin is at high impedance, and
the device is in standby state.
VLOGIC
VLOGIC is an input pin that supplies an internal level translator
for serial bus operation from 1.2V to 5.5V.
Principles of Operation
The ISL23418 is an integrated circuit incorporating one DCP with
its associated registers and an SPI serial interface providing
direct communication between a host and the potentiometer.
The resistor array is composed of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper. The electronic switches on the device operate in a
“make before break” mode when the wiper changes tap
positions.
Voltage at any DCP pins, RH, RL, or RW should not exceed V_CC
level at any conditions during power-up and normal operation.
The V_LOGIC pin must be connected to the SPI bus supply, which
allows reliable communication with a wide range of
microcontrollers, independently of the V_CC level. This is
extremely important in systems in which the digital supply has
lower levels than the analog supply.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(RH and RL pins). The RW pin of the DCP is connected to
intermediate nodes and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by the 8-bit volatile Wiper Register
(WR). When the WR of a DCP contains all zeroes (WR[7:0] = 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL). When
the WR register of a DCP contains all ones (WR[7:0] = 7Fh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As the
value of WR increases from all zeroes (0) to all ones (127
decimal), the wiper moves monotonically from the position
closest to RL to the position closest to RH. At the same time, the
resistance between RW and RL increases monotonically, while
the resistance between RH and RW decreases monotonically.
While the ISL23418 is being powered up, the WR is reset to 40h
(64 decimal), which locates RW to the mid value between RL and
RH.
WR can be read or written to directly using the SPI serial
interface as described in the following sections.
Memory Description
The ISL23418 contains two volatile 8-bit registers: the Wiper
Register (WR) and the Access Control Register (ACR). A memory
map of ISL23418 is shown in Table 1. WR, at address 0, contains
the current wiper position of the DCP. ACR, at address 10h,
contains information and control bits as described in Table 2.
ADDRESS
(hex)
10
0
TABLE 1. MEMORY MAP
VOLATILE
DEFAULT SETTING
(hex)
ACR
40
WR
80
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7
6
5
4
3
2
1
0
NAME 0 SHDN 0
0
0
0 SDO 0
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, DCP is forced to
end-to-end open circuit, and RW is connected to RL through a
2kΩ serial resistor, as shown in Figure 25. Default value of the
SHDN bit is 1.
13
FN7901.0
August 3, 2011