ISL23418 Datasheet, PDF (14/20 Pages) Intersil Corporation – Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23418
RH
RW
2kΩ
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
In shutdown mode, the RW terminal is shorted to the RL terminal
with around 2kΩ resistance, as shown in Figure 25. When the device
enters shutdown, all current DCP WR settings are maintained. When
the device exits shutdown, the wipers return to the previous WR
settings after a short settling time (Figure 26).
POWER-UP
MID SCALE = 40H
USER PROGRAMMED
AFTER SHDN
SHDN ACTIVATED ^{SHDN RELEASED}
WIPER RESTORE TO
ORIGINAL POSITION
SHDN MODE
0
TIME (s)
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
In shutdown mode, if there is a glitch in the power supply that
causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the
wipers are RESET to their mid position. This is done to avoid an
undefined state at the wiper outputs.
SPI Serial Interface
The ISL23418 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output, with data
clocked in on the rising edge of SCK and clocked out on the
falling edge of SCK. CS must be LOW during communication with
the ISL23418. The SCK and CS lines are controlled by the host or
master. The ISL23418 operates only as a slave device. All
communication over the SPI interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
The SPI protocol contains an Instruction Byte followed by one or
more Data Bytes. A valid Instruction Byte contains instruction as
the three MSBs, with the following five register address bits
(Table 3). The next byte sent to the ISL23418 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT
BIT # 7
6
5
4
3
2
1
0
I2
I1
I0 R4 R3 R2 R1 R0
Table 4 contains a valid instruction set for ISL23418. If the
[R4:R0] bits are zero, then the read or write is to the WR register. If
the [R4:R0] bits are 10000, then the operation is to the ACR.
Write Operation
A write operation to the ISL23418 is a two or more bytes
operation. It first requires CS to transition from HIGH to LOW.
Then the host sends a valid Instruction Byte to the SDI pin,
followed by one or more Data Bytes. The host terminates the
write operation by pulling the CS pin from LOW to HIGH. The
instruction is executed on the rising edge of CS (Figure 27).
Read Operation
A read operation to the ISL23418 is a four-byte operation. First,
the CS transitions from HIGH to LOW. Then the host sends a valid
Instruction Byte to the SDI pin, followed by a “dummy” Data Byte,
an NOP Instruction Byte, and another “dummy” Data Byte. The
SPI host receives the Instruction Byte (instruction code + register
address) and the requested Data Byte from the SDO pin on the
rising edge of SCK during the third and fourth bytes, respectively.
The host terminates the read by pulling the CS pin from LOW to
HIGH (Figure 28).
I2
I1
I0
0
0
0
0
0
1
0
1
1
1
0
0
1
1
0
where “X” means “do not care.”
INSTRUCTION SET
R4
R3
X
X
X
X
X
X
R4
R3
R4
R3
TABLE 4. INSTRUCTION SET
R2
R1
R0
X
X
X
X
X
X
X
X
X
R2
R1
R0
R2
R1
R0
NOP
ACR READ
ACR WRTE
WR or ACR READ
WR or ACR WRTE
OPERATION
14
FN7901.0
August 3, 2011